1. EE40 Lec 20 MOS Circuits Reading: Chap. 12 of Hambley
Supplement reading on MOS Circuits

2. Small-signal equivalent circuits Examples:
OUTLINE
Bias circuits
Small-signal equivalent circuits
Examples:
Common source amplifier
Source follower
Common gate amplifier
Digital Gates
CMOS
EE40, Fall Prof. White

3. Bias Circuits Use load line to find Quiescent operating point.
Remember no current flow through the gate.
Fixed-plus Self-Bias CKT
VDD RD
VG+vin
VDD RD R1 R2 RS

4. Steps for MOSFET Circuit Analysis
1) Look at DC case to find Q point
Use load line technique
All capacitors are open circuit, Inductors are short circuit
Determine Q-point, get gm and rd for small signal AC model
2) AC Small signal analysis
DC source is ac ground (because there is no AC signal variation).
All capacitors are approximated as short circuit (unless otherwise specified).

5. Example: Common Source Amplifier
VDD RD C R1 + - vo C RL VG + -
vin + -
v(t) R2 RS C

6. Step 1: find Q point VDD RD C R1 + C vo VG RL VDS - + + vin R2 v(t) RS
Not connected
for DC component RD C R1 + - vo C VG RL
VDS + -
vin + -
v(t) R2 RS C
Not connected
for DC component

7. Load line to determine Q Point by graphical method
Loadline to determine VGSQ
Loadline to determine VDSQ
VGSQ
From load lines, we get ID  and hence gm and rd

8. Load line to determine Q Point by analytical method
Solve VGSQ assume saturation region first
IDQ is known, then solve VDSQ
Check VDSQ value is consistent with saturation region ( i.e. VDS> VGSQ-Vt)
From load lines, we get ID  and hence gm and rd

9. Determination of gm and rd graphically
Example: Q point is known to be VGS=2.5V, VDS=6V

10. Determination of gm and rd by Analytical Models
In Saturation Region
In Triode Region

11. Small Signal Model Inverting For output impedance Rout:
Turn off all independent sources.
Take away load impedance RL

12. Example: Source Follower
VDD R1 C VG C + -
vin RL + - vo + -
v(t) R2 RS

13. Step 1: find Q point
VDD R1 C VG C + -
vin RL + - vo + -
v(t) R2 RS

14. Small Signal Model Rout is small For output impedance Rout:
Non-inverting,
Voltage Gain <1
Rin high
Current gain can be high
For output impedance Rout:
Turn off all independent sources.
Take away RL
Add Vx and find ix
Rout is small

15. Example: Common Gate Amplifier
VDD RD C + - vo VG RL C + -
vin + -
v(t) RS
-VSS

16. Step 1: find Q point
VDD RD C + - vo VG RL C + -
vin + -
v(t) RS
-VSS

17. Load line
The only difference in all three circuits are the intercepts at the axes.
Again from load lines, we get ID  and hence gm and rd

18. Small Signal Model Non-inverting For output impedance Rout:
Turn off all independent sources.
Take away RL
Add Vx and find ix

19. Logic Gates : Pull-Up and Pull-Down
PMOS or Resistor
NMOS or Resistor

20. Inverter = NOT Gate Vin Vout Ideal Transfer Characteristics Vout Vin

21. NMOS Inverter: Resistor Pull-Up
Circuit:
Voltage-Transfer Characteristic
vOUT
VDD F A iD
vIN = VDD
increasing
vGS = vIN > VT
vIN VT
VDD
VDD/RD
VDD A F 1
vDS
vGS = vin  VT

22. Output is low only if both inputs are high
NMOS NAND Gate
Output is low only if both inputs are high
VDD RD F A
Truth Table A B F 1 B

23. Output is low if either input is high
NMOS NOR Gate
Output is low if either input is high
VDD RD F A B
Truth Table A B F 1

24. Disadvantages of NMOS Logic Gates
Large values of RD are required in order to
achieve a low value of VLOW
keep power consumption low
Large resistors are needed, but these take up a lot of space.

25. CMOS Inverter: Intuitive Perspective
CIRCUIT
SWITCH MODELS
VDD
VIN
VOUT S D G
VDD
VDD Rp
VOUT
VOUT
VOL = 0 V
VOH = VDD Rn
Low static power consumption, since
one MOSFET is always off in steady state
VIN = VDD
VIN = 0 V

26. The CMOS Inverter: Current Flow
N: sat
P: sat
VOUT i
N: off
P: lin C V DD
VDD S G
N: sat
P: lin D I
VIN
VOUT A B D E D G
N: lin
P: sat S
N: lin
P: off
VIN
VDD

27. Power Dissipation: Direct-Path Current
VDD V
VDD-VT DD
vIN: S G VT D i
vIN
vOUT
Ipeak D G i: S
tsc
time
Energy consumed per switching period:

28. CMOS NAND Gate
VDD A B F 1 A B
Notice that the pull-up network is related to the pull-down network by DeMorgan’s Theorem! F A
NMOS, Pull-down
PMOS, Pull-up B

29. CMOS NOR Gate
VDD A B F 1 A
Notice that the pull-up network is related to the pull-down network by DeMorgan’s Theorem! B F
NMOS, Pull-down
PMOS, Pull-up B A

30. Multiple Input NOR Gate

31. Features of CMOS Digital Circuits
The output is always connected to VDD or GND in steady state
Full logic swing; large noise margins
Logic levels are not dependent upon the relative sizes of the devices (“ratioless”)
There is no direct path between VDD and GND in steady state
no static power dissipation