GROUP 2 CHAPTER 16 CONTROL UNIT Group Members ๏ Evelio L. Hernandez ๏ Ashwin Soerdien ๏ Andrew Keiper ๏ Hermes Andino

MICRO-OPERATIONS Micro-Operations are the functional, or atomic, operations of a processor Execution of a program includes these cycles: Fetch Indirect Execute Interrupt Each instruction is executed during an instruction cycle made up of shorter sub- cycles Each step is very simple and does very little

Program Execution

The FETCH CYCLE Memory Address Register (MAR) Connected to address bus Specifies address for read or write operation Memory Buffer Register (MBR) Connected to data bus Holds data to write or last data read Program Counter (PC) Holds address of next instruction to be fetched Instruction Register (IR) Holds last instruction fetched

FETCH SEQUENCE Fetch the instruction from RAM whose RAM address is in the PC register and place it in the IR register in the processor. Increment the value in the PC register by the length of the currently fetched instruction so that the PC now contains the address of the next instruction in sequence in RAM. Decode and execute the instruction in the IR register

FETCH Diagram

FETCH SEQUENCE symbolic t1:(PC) -> MAR t2:(Memory) -> MBR (PC) +1 -> PC t3:(MBR) -> IR Or t1: MOV (PC), MAR t2: Increment PC t3: MOV (RAM), MBR t4: MOV (MBR), IR

Rules for Clock Cycle Grouping Proper sequence must be followed PC -> MAR must precede (Memory) -> MBR Conflicts must be avoided Must not read & write same register at same time (Memory) -> MBR & (MBR) -> IR must not be in same cycle Also: (PC) +1 -> PC involves addition Use ALU May need additional micro-operations

INDIRECT CYCLE (IR address ) -> MAR (from address field of IR) (Memory) -> MBR (MBR address ) -> IR address Now the: MBR contains an address IR is now in same state as if direct addressing had been used

INTERRUPT CYCLE Interrupt provides a way to temporarily suspend normal program execution so the CPU can be freed to service other requests. t1: (PC) -> MBR t2: save-address -> MAR routine-address -> PC t3: (MBR) -> Memory Routine address: address of the interrupt process

EXECUTE CYCLE add Different for each instruction Example: ADD R1, X Add the contents of location X to Register 1, and store result in Register 1 t1:(IR address ) –> MAR t2:(Memory) –> MDR t3:R1 + MDR –> R1 Micro-operations do not overlap

EXECUTE CYCLE isz ISZ X Increment and skip if zero t1: IR(address) –> MAR t2: (Memory) –> MBR t3: (MBR) + 1 –> MBR t4: (MBR) –> Memory if (MBR) == 0 thenPC + 1 –> PC “if” is a single micro-operation Both micro-operations performed during t4

EXECUTE CYCLE bsa BSA X : Branch and Save Address Address of the instruction following BSA is saved in X Execution continues from x+1 t1: IR(address) –> MAR (PC) -> MBR t2: IR(address) –> PC (MBR) -> Memory t3: PC + 1 -> PC

INSTRUCTION CYCLE Each phase is broken down into sequence of fundamental micro-operations Example of cycles: fetch, indirect, interrupt Execute cycle Each opcode has one sequence of micro-operations Sequences need to be tied together Assume a “new” 2-bit register Instruction Cycle Code (ICC) designates which part of cycle processor is in 00: Fetch 01: Indirect 10: Execute 11: Interrupt

INSTRUCTION CYCLE: flowchart

Functional Requirements Define the basic elements of the processor Describe the micro-operations of the processor Determine the functions the control unit must perform

THE PROCESSOR Arithmetic Logic Unit (ALU) Registers Internal and External Data Paths Control Unit

MICRO-OPERATIONS types Transfer data between registers Transfer data from registers to external world Transfer data from external world to register Perform arithmetic or logical operations

CONTROL UNIT functions Sequencing Causing the processor to step through a series of micro-operations Execution Causing the performance of each micro- operation Done using Control Signals

CONTROL SIGNALS Clock One micro-instruction (or set of parallel micro-instructions) per clock cycle Instruction register Holds the current op-code Determines which micro-instructions are performed Flags State of CPU Results of previous operations

Model of CONTROL UNIT

CONTROL SIGNALS output Within CPU Cause data movement Activate specific functions Via control bus To memory To I/O modules

Control Signal Sequence Fetch Example (PC) -> MAR Control unit activates signal to open gates between PC and MAR (Memory) -> MBR Open gates between MAR and address bus Memory reads control signal Open gates between data bus and MBR

Data Paths and Control Signals

Internal Organization Usually a single internal bus Gates control movement of data onto and off the bus Control signals control data transfer to and from external systems bus Temporary registers needed for proper operation of ALU

CPU with Internal Bus

Intel 8085 CPU Block Diagram

Intel 8085 Pin Configuration

Intel 8085 OUT Instruction Timing Diagram

Hardwired Implementation (1) Control unit inputs Flags and control bus Each bit means something Instruction register Op-code causes different control signals for each different instruction Unique logic for each op-code Decoder takes encoded input and produces single output n binary inputs and 2 n outputs

Hardwired Implementation (2) Clock Repetitive sequence of pulses Useful for measuring duration of micro-operations Must be long enough to allow signal propagation Different control signals at different times within instruction cycle Need a counter with different control signals for t1, t2 etc.

Control Unit with Decoded Inputs

Problems with Hard Wired Designs Complex sequencing and micro-operation logic Difficult to design and test Inflexible design Difficult to add new designs

Review Questions 1. Explain the distinction between the written sequence and the time sequence of an instruction. 2. What is the relationship between instructions and micro-operations? 3. What is the overall function of a processor's control unit? 4. What basic tasks does a control unit perform? 5. What are the cycles on the execution of a program? 6. List three types of control signals. 7. Provide a typical list of the I/O of a control unit. 8. Describe the interrupt cycle. 9. Outline the Indirect cycle steps. (Symbols)