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Introduction to Computer Organization and Architecture Micro Program ภาษาเครื่อง ไมโครโปรแกรม.

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Presentation on theme: "Introduction to Computer Organization and Architecture Micro Program ภาษาเครื่อง ไมโครโปรแกรม."— Presentation transcript:


2 Introduction to Computer Organization and Architecture Micro Program ภาษาเครื่อง ไมโครโปรแกรม

3 Model of Control Unit How the Control Unit Generate the control signal?

4 Model of Control Unit  Get instruction from Instruction Register  Working steps with the timing generator and conditions from flag, the signal from IR passed through the Decoder circuit into the CU to generate the control signal out.

5 Block Diagram of the Control Unit

6 Control Unit with Decoded Inputs

7 Microprogr ams ? 1950 Maurice V. Wikes ( Cambridge Univer.) IBM System/360 to achieve instruction- set compatibility across many models. MicroprogramsMicroprogramming allows a CPU’s program control unit : PCU to be designed sequences known as Microprograms are placed in a special control memory in the CPU.

8 Wilkes's Microprogrammed Control Unit

9 - so that instruction from the CPU’s main instruction set is executed by invoking and executing the corresponding microprogram. * * * * * * * CPU with no floating- point arithmetic circuits can execute by means of fixed- point arithmetic circuits. Microprogr ams ?

10 Digital Systems : CPU  Data Path Unit network of functional and storage units capable of performing certain operation on data words.  Control Unit issue control signal to the data path for selecting the function to be performed at specific times and route through the appropriate parts of the datapath unit.

11 Data Paths and Control Signals

12 Digital Systems : CPU  Hardwired fixed logic circuits to generate the control signals.  Microprogrammed microprograms stores the control signals in sequence of micro-instructions (microprograms) in a control memory. * provide a systematic & flexible method *

13 Microprogramme d Control Use microprograms to select, interpret, and execute instruction set. CU contain logic to generate micro- instruction addresses and to fetch and decode from control memory. Fig. 15.4

14 Control Unit Microarchitecture

15 Basic Concepts Instruction is implemented by a sequence of one or more sets of concurrent micro- operations. Each micro-operation is associated with a group of control lines that must be activated in a prescribed sequence to trigger the micro- operations.

16 Basic Concepts Program Execution Instructi on Cycle Instructi on Cycle... Fet ch Exec ute Inter rupt mOPmOP mOPmOP mOPmOP...

17 Basic Concepts Microprogramming is a method of control-unit design in which the control signal selection and sequencing information is stored in a ROMRAM ROM or RAM called..... Control Memory Control Memory : CM

18 Functioning of Microprogrammed Control Unit

19 Basic Concepts control signals activated micro- instruction, The control signals could be activated at any time that are specified by a micro- instruction, which is fetched from CM in much the same way an instruction is fetched from main memory.

20 Basic Concepts Instruction Cycle Fetch Indirect Execute Interrupt

21 Flowchart for Instruction Cycle


23 Basic Concepts Fetch Cycle Fetch Cycle 3 steps and 4 micro-operations t 1 : MAR <--- (PC) t 2 : MBR <--- Memory I PC <--- (PC) + I t 3 : IR <--- (MBR) I I : Instruction Length

24 Sequence of Events, Fetch Cycle

25 Basic Concepts Indirect Cycle Indirect Cycle 3 micro-operations t 1 : MAR <--- (IR (address)) t 2 : MBR <--- Memory t 3 : IR(Address) <--- (MBR (address) )

26 Basic Concepts Execute Cycle Execute Cycle vary on op-code such as ADD R1, X will have 3 micro-operations t 1 : MAR <--- (IR(address)) t 2 : MBR <--- Memory t 3 : R1 <--- (R1) + (MBR)

27 Basic Concepts Execute Cycle Execute Cycle as ISZ X (Increment and Skip instruction) t 1 : MAR <--- (IR(address)) t 2 : MBR <--- Memory t 3 : MBR <--- (MBR) + 1 t 4 : Memory <--- (MBR) If ((MBR) = 0) then (PC <--- (PC)+1)

28 Basic Concepts Execute Cycle Execute Cycle as BSA X (subroutine call : Branch-and-save- address instruction) t 1 : MAR <--- (IR(address)) MBR <--- (PC) t 2 : PC <--- (IR(address)) Memory <--- (MBR) t 3 : PC <--- (PC) + 1

29 Basic Concepts Interrupt Cycle Interrupt Cycle 3 micro-operations t 1 : MBR <--- (PC) t 2 : MAR <--- Save_Address PC <--- Routine_Address t 3 : Memory <--- (MBR)

30 Basic Concepts Each micro-instruction also explicitly or implicitly specifies the next micro-instruction to be used, thereby providing the necessary information for micro-operation sequencing. set of micro- instruction for ms micropr ogram

31 Organization of Control Memory

32 Microinstructio n Encoding


34 Basic Concepts Advantage flexible Advantage Microprogram can be changed relatively easily by changing the contents of CM. (flexible) Disadvantage Disadvantage The time required to access the microinstructions from CM. Chip area and circuit delay must both be minimized. Used in CISC’s as the Pentium and MC680X0

35 Micro- instructions  Horizontal Formats long formats, little encoding of the control fields, and the ability to control many micro- operation in parallel.  Vertical Formats short formats, considerable control- field encoding, and limited parallelism. interpreted by nano- instruction that directly control the hardware.


37 Micro-instruction Types Each micro-instruction specifies single (or few) micro-operations to be performed — (vertical micro-programming) Each micro-instruction specifies many different micro-operations to be performed in parallel —(horizontal micro-programming)

38 Vertical Micro-programming Width is narrow n control signals encoded into log 2 n bits Limited ability to express parallelism Considerable encoding of control information requires external memory word decoder to identify the exact control line being manipulated

39 Horizontal Micro-programming Wide memory word High degree of parallel operations possible Little encoding of control information

40 Alternative Microinstructio n Formats for a Simple Machine


42 Next Address Decision Depending on ALU flags and control buffer register —Get next instruction –Add 1 to control address register —Jump to new routine based on jump microinstruction –Load address field of control buffer register into control address register —Jump to machine instruction routine –Load control address register based on opcode in IR

43 Functioning of Microprogrammed Control Unit

44 Design Considerations Size of microinstructions Address generation time —Determined by instruction register –Once per cycle, after instruction is fetched —Next sequential address –Common in most designed —Branches –Both conditional and unconditional

45 Sequencing Techniques Based on current microinstruction, condition flags, contents of IR, control memory address must be generated Based on format of address information —Two address fields —Single address field —Variable format

46 Branch Control Logic: Two Address Fields

47 Branch Control Logic: Single Address Field

48 Branch Control Logic: Variable Format

49 Address Generation ExplicitImplicit Two-fieldMapping Unconditional BranchAddition Conditional branchResidual control

50 Execution The cycle is the basic event Each cycle is made up of two events —Fetch –Determined by generation of microinstruction address —Execute

51 Execute Effect is to generate control signals Some control points internal to processor Rest go to external control bus or other interface

52 Control Unit Organization

53 A Taxonomy of Microinstructions Vertical/horizontal Packed/unpacked Hard/soft microprogramming Direct/indirect encoding

54 How to Encode K different internal and external control signals Wilkes’s: —K bits dedicated —2K control signals during any instruction cycle Not all used —Two sources cannot be gated to same destination —Register cannot be source and destination —Only one pattern presented to ALU at a time —Only one pattern presented to external control bus at a time Require Q < 2K which can be encoded with log2Q < K bits Not done —As difficult to program as pure decoded (Wilkes) scheme —Requires complex slow control logic module Compromises —More bits than necessary used —Some combinations that are physically allowable are not possible to encode

55 Specific Encoding Techniques Microinstruction organized as set of fields Each field contains code Activates one or more control signals Organize format into independent fields —Field depicts set of actions (pattern of control signals) —Actions from different fields can occur simultaneously Alternative actions that can be specified by a field are mutually exclusive —Only one action specified for field could occur at a time

56 Microinstructio n Encoding


58 Micro- instructions Machine instruction is executed by a microprogram which acts as a real-time interpreter for the instruction. Microinstruction Format IBM System/370 Model 145 Cont rol Opera nd1 Opera nd2 CM Addressin g 081616 2424 3131

59 IBM 3033 Microinstruction Format

60 Other Samples LSI computer

61 Simplified Block Diagram of the LSI-11 Processor

62 Organization of the LSI-11 Control Unit

63 LSI-11 Microinstruction Format

64 Introduction to Computer Organization and Architecture Machine Language ภาษาเครื่อ ง

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