1. Chapter 14 Control Unit Operation

2. Contents Micro-Operation Control of the Processor
Hardwired Implementation

3. Micro-Operations
Micro-Operations
Micro refers to the fact that each step is very simple and accomplishes very little
The execution of a program consists of the sequential execution of instructions
Each instruction is executed during an instruction cycle made up of shorter subcycles
The performance of each subcycle involves one or more shorter operations, that is, micro-operations

4. Constituent Element
Micro-Operations

5. The Fetch Cycle Four involved registers.
Micro-Operations
Four involved registers.
Memory address register (MAR) : Is connected to the address lines of the system bus. It specifies the address in memory for a read or write operation.
Memory buffer register (MBR) : Is connected to the data lines of the system bus. It contains the value to be stored in memory or the last value read from memory.
Program counter (PC) : Holds the address of the next instruction to be fetched.
Instruction register (IR) : Holds the last instruction fetched.

6. Sequence of Events, Fetch Cycle
Micro-Operations
(a) Beginning

7. Sequence of Events, Fetch Cycle
Micro-Operations
(b) First Step

8. Sequence of Events, Fetch Cycle
Micro-Operations
(c) Second Step

9. Sequence of Events, Fetch Cycle
Micro-Operations
(d) Third Step

10. The Fetch Cycle – Sequence
Micro-Operations
Beginning : the address of the next instruction to be executed is in the PC
First step : move that address to the MAR
Second step : bring in the instruction. The desired address is placed on the address bus, the control unit issues a READ command on the control bus, and the result appears on the data bus and is copied into the MBR.
Third step : move the contents of the MBR to the IR. This free up the MBR for use during a possible indirect cycle.

11. The Fetch Cycle – Sequence
Micro-Operations
• Symbolic presentation
t1: MAR  (PC)
t2: MBR  Memory
PC  (PC) + I
t3: IR  (MBR)
• Micro-operation grouping rules
The proper sequence of events must be followed.
Conflicts must be avoided.
• Micro-operation involve an addition
This addition could be performed bye the ALU.
The use of the ALU may involve additional micro-operations.

12. The Indirect Cycle Indirect addressing t1: MAR  (IR(Address))
Micro-Operations
Indirect addressing
t1: MAR  (IR(Address))
t2: MBR  Memory
t3: IR(Address)  (MBR(Address))

13. The Interrupt Cycle t1: MBR  (PC) t2: MAR  Save_Address
Micro-Operations
t1: MBR  (PC)
t2: MAR  Save_Address
PC  Routine_Address
t3: Memory  (MBR)

14. The Execute Cycle ADD R1, X ISZ X t1: MAR  (IR(address))
Micro-Operations
ADD R1, X
t1: MAR  (IR(address))
t2: MBR  Memory
t3: R1  (R1) + (MBR)
ISZ X
t3: MBR  (MBR) + 1
t4: Memory  (MBR)
If((MBR) = 0) then (PC  (PC) +I)

15. The Execute Cycle BSA X t1: MAR  (IR(address)) MBR  (PC)
Micro-Operations
BSA X
t1: MAR  (IR(address))
MBR  (PC)
t2: PC  (IR(address))
Memory  MBR
t3: PC  (PC) + I

16. The Instruction Cycle
Micro-Operations
There is one sequence each for the fetch, indirect, and interrupt cycle, and, for the execute cycle, there is one sequence of micro-operation for each opcode
Instruction cycle code(ICC)
00: Fetch
01: Indirect
10: Execute
11: Interrupt

17. Flowchart for Instruction Cycle
Micro-Operations

18. Functional Requirements
Control Of The Processor
The following three-step process leads to a characterization of the control unit:
Define the basic elements of the processor
Describe the micro-operations that the processor performs
Determine the functions that the control unit must perform to cause the micro operations to be performed
Basic functional elements
ALU
Register
Internal data paths
Control unit

19. Functional Requirements
Control Of The Processor
The reader should see that all micro-operations fall into the following categories
Transfer data from one register to another
Transfer data from a register to an external interface
Transfer data from an external interface to a register
Perform an arithmetic or logic operation, using registers for input and output
The control unit perform two basic tasks
Sequencing
Execution

20. Control Of The Processor
Control Signals
Control Of The Processor
Inputs
Clock
Instruction register
Flags
Outputs
Control signals within the processor
Control signals to control bus

21. Control Of The Processor
Model of Control Unit
Control Of The Processor

22. Control Of The Processor
Control Signals
Control Of The Processor
A control signal that opens gates, allowing the contents of the MAR onto the address bus
A memory read control signal on the control bus
A control signal that opens the gates, allowing the contents of the data bus to be stored in the MBR
Control signals to logic that add 1 to the contents of the PC and store the result back to the PC

23. A Control Signals Example
Control Of The Processor
Control signals go to three separate destinations
Data paths
ALU
System bus

24. Data Paths and Control Signals
Control Of The Processor

25. Micro-operation and Control Signals
Control Of The Processor

26. Internal Processor Organization
Control Of The Processor
The ALU and all processor registers are connected by a single internal bus
Gates and control signals are provided for movement of data onto and off the bus from each register
Two new register,labeled Y and Z, have been added to the organization

27. Internal Processor Organization
Control Of The Processor
An operation to add a value from memory to the AC would have the following steps:
t1: MAR<-(IR(address))
t2: MBR<-Memory
t3: Y<-(MBR)
t4: Z<-(AC) + (Y)
t5:AC<-(Z)

28. Control Of The Processor
CPU with Internal Bus
Control Of The Processor

29. Control Of The Processor
The Intel 8085
Control Of The Processor
Incrementer/decrementer address latch
Logic that can add 1 to or subtract 1 from the contents of the stack pointer or program counter
Interrupt control
This module handles multiple levels of interrupt signals
Serial I/O control
This module interfaces to devices that communicate 1 bit at a time

30. Intel 8085 CPU Block Diagram
Control Of The Processor

31. Intel8085 External Signals
Control Of The Processor

32. Intel 8085 External Signals
Control Of The Processor

33. Intel 8085 Pin Configuration
Control Of The Processor

34. Control Of The Processor
Timing Diagram
Control Of The Processor

35. Hardwired Implementation
Control unit implementation
Hardwired implementation
Microprogrammed implementation

36. Hardwired Implementation
Control Unit Inputs
Hardwired Implementation
The key inputs are the instruction register, the clock, flags, and control bus signals
To simplify the control unit logic, there should be a unique logic input for each opcode
Decoder
Takes an encoded input and produces a single output
The clock portion of the control unit issues a repetitive sequence of pulses

37. Hardwired Implementation
Decoder
Hardwired Implementation

38. Control Unit with Decoded Inputs
Hardwired Implementation

39. Hardwired Implementation
Control Unit Logic
Hardwired Implementation
Derive a Boolean expression of that signal as a function of the inputs
Define two new control signal, P and Q
PQ = 00 Fetch Cycle
PQ = 01 Indirect Cycle
PQ = 10 Execute Cycle
PQ = 11 Interrupt Cycle

40. Hardwired Implementation
Control Unit Logic
Hardwired Implementation
The task of implementing a combinatorial circuit that satisfies all of these equations becomes extremely difficult
The results is that a far simpler approach
Microprogramming