1 DMT 121 – ELECTRONIC DEVICES CHAPTER 5: FIELD-EFFECT TRANSISTOR (FET)

2 1. Junction Field-Effect Transistor (JFET) N-channel P-channel 2. Metal Oxide Semiconductor Field- Effect Transistor (MOSFET) Enhancement-MOSFET Depletion-MOSFET TYPES OF FET

3 FET vs BJT FETBJT Unipolar device – operate use only one type of charge carrier Bipolar device – operate use both electron & hole Voltage-controlled device – voltage between gate & source control the current through device. Current-controlled device – base current control the amount of collector current. High input resistanceHigh input impedance Slower in switching (turn- on & off) Faster in switching (turn- on & off)

4 THE JFET BJT – current controlled, I C is direct function of I B FET – voltage controlled, I D is a direct function of the voltage V GS applied to the input circuit. FIGURE: (a) Current-controlled and (b) voltage-controlled amplifiers.

5 JFET 3 terminal: Drain – upper end Source – lower end Gate – 2 p/n-type regions are diffuse in the n/p-type material to form a channel. FIGURE: A representation of the basic structure of the two types of JFET.

6 JFET Structures & Symbols JFET StructuresJFET Symbols

7 Basic Operation of JFET V DD provides a drain-to-source voltage and supplies current from drain to source. V GG sets the reverse-bias voltage between gate and source. JFET is always operated with the gate-source pn junction reverse- biased. Reverse-biased of gate-source junction with negative gate voltage produce a depletion region along pn junction – increase resistance by restricting the channel width

8 Basic Operation of JFET Figure: Greater V GG narrows the channel (between the white areas) which increases the resistance of the channel and decreases I D. Figure: Less V GG widens the channel (between the white areas) which decreases the resistance of the channel and increases I D.

9 Basic Operation of JFET The channel width and the channel resistance can be controlled by varying the gate voltage – controlling the amount of drain current, I D. The depletion region (white area) created by reverse bias. Wider toward the drain-end of the channel – reverse- bias voltage between gate and drain is greater than voltage between gate and source.

10 JFET Analogy JFET operation can be compared to a water spigot. The source The source of water pressure is the accumulation of electrons at the negative pole of the drain-source voltage. The drain The drain of water is the electron deficiency (or holes) at the positive pole of the applied voltage. The control The control of flow of water is the gate voltage that controls the width of the n-channel and, therefore, the flow of charges from source to drain.

11 JFET Characteristic Figure: Drain CharacteristicFigure: JFET with V GS =0 V and variable V DS (V DD )

12 JFET Characteristics and Parameters, V GS = 0 V GS = 0 V by shorting the gate to source (both grounded). I D increases proportionally with increases of V DD (V DS increases as V DD is increased). This is called the ohmic region (point A to B). In this area (ohmic region) the channel resistance is essentially constant because of the depletion region is not large enough to have sufficient effect  V DS and I D are related by Ohm’s law In JFET, IG = 0  an important characteristic for JFET

13 JFET Characteristics and Parameters, V GS = 0 At point B, the curve levels off and enter the active region where I D constant. Value of V DS at which I D becomes constant is pinch-off voltage, V P. As V DD increase from point B to point C, the reverse-bias voltage from gate to drain (V GD ) produces a depletion region large enough to offset the increase in V DS, thus keeping I D relatively constant. V DS increase above V P, produce almost constant I D called I DSS. IDSS (drain to source current with gate shorted) is max drain current at V GS = 0V

14 JFET Characteristics and Parameters, V GS = 0 Breakdown occurs at point C when I D begins to increase very rapidly with any further increase in V DS. It can result irreversible damage to the device So JFETs are always operated below breakdown and within the constant- current area (between points B and C on the graph)

15 V GS controls I D

16 As V GS is set to increasingly more negative by adjusting V GG. A family of drain characteristic curves is produced. Notice that I D decrease as the magnitude of V GS is increased to larger negative value  narrowing of channel. For each increase in V GS, the JFET reaches pinch- off (constant current begins) at values of V DS less than V P. The amount of drain current is controlled by V GS. V GS controls I D

17 Cutoff Voltage Value of V GS that makes ID ≈ 0A is the cutoff voltage, V GS (off). JFET must operated between V GS =0V and V GS (off). In n-channel JFET: V GS has large –ve value, I D is reduce to zero. Cutoff effect due to widening of depletion region.

18 V GS controls I D

19 Pinch-Off & Cutoff Voltage Pinch-off voltage, V P = value of V DS at which drain current becomes constant and equal to I DSS at V GS = 0V Pinch-off occurs for V DS value less than V P when V GS is nonzero. V GS (off) & V P are equal in magnitude but opposite sign V GS (off) = -V P

20 P-channel JFET operation Same as n-channel JFET except required negative V DD and positive V GS.

21 EXAMPLE V GS (off)= -4V and I DSS = 12mA. Determine the minimum value of V DD required to put the device in constant- current region of operation when V GS = 0V.

22 JFET Transfer Characteristic

23 constant Control Variable Constant Control Variable JFET Transfer Characteristic The transfer characteristic of input-to-output is not as straightforward in a JFET as it is in a BJT. In a BJT,  indicates the relationship between I B (input) and I C (output). I C =  I B In a JFET, the relationship of V GS (input) and I D (output) is a little more complicated:

24 JFET Transfer Curve This graph shows the value of I D for a given value of V GS. When V GS = 0; I D = I DSS When V GS = V GS (off) = V P ; I D = 0 mA

25 Plotting JFET Transfer Curve Solving for V GS = 0VI D = I DSS Step 1 Solving for V GS = V p (V GS(off) ) I D = 0A Step 2 Solving for V GS = 0V to V p Step 3

26 EXAMPLE JFET with I DSS = 9 mA and V GS (off) = -8V (max). Determine I D for V GS = 0V, -1V and -4V. ANSWER: V GS = 0V, I D = 9mA V GS = -1V, I D = 6.89mA V GS = -4V, I D = 2.25mA

27 JFET Biasing Just as we learned that the bipolar junction transistor must be biased for proper operation, the JFET too must be biased for operation. Let’s look at some of the methods for biasing JFETs. In most cases the ideal Q- point will be the middle of the transfer characteristic curve which is about half of the IDSS. JFET I D = I S I G  0 A BJT I C =  I B I C  I E V BE  0.7 V

28 JFET Biasing JFET must be operated that gate-source junction is always reverse-biased. V G =0V

29 Self-Bias Since V G = 0V, I G = 0A I S = I D V S = I D R S V GS = V G – V S = 0 – I D R S = -I D R S V D = V DD – I D R D V DS = V D – V S = V DD – I D (R D + R S )

30 JFET Biasing, Fixed- Bias Configuration I G = 0 so V RG = I G R G = (0 A)R G = 0 then R G can be removed from the circuit. R G only need in ac analysis through the input V i - V GG – V GS = 0 V GS = - V GG

31 JFET Biasing, Fixed- Bias Configuration Fig. 7.5 Measuring the quiescent values of I D and V GS. Drain-to-source voltage can be determined by applying Kirchoff’s voltage law V DS + I D R D –V DD = 0 V DS = V DD – I D R D Source voltage to ground; V S = 0 Drain-to-source voltage can also be determined through; V DS = V D – V S but V S = 0 then V DS = V D Gate-to-source voltage V GS = V G – V S ; since V S = 0 V GS = V G Since the configuration requires two dc supply, its use is limited and not included in the list of common FET configurations.

32 JFET Biasing, Self- Bias Configuration Most common type of JFET bias. Eliminates the need for two dc supplies. The controlling gate-to-source is determined by the voltage across a resistor R S. For analysis, resistor R G replaced by a short circuit equivalent since I G = 0 A.

33 JFET Biasing, Self- Bias Configuration Voltage drop across source resistor, R S V RS = I S R S ; since I S = I D then V RS = I D R S For indicated closed loop in the Figure 7.9 -V GS – V RS = 0 V GS = - V RS V GS = -I D R S Drain current, I D : Fig. 7.9 DC analysis of the self-bias configuration.

34 JFET Biasing, Self- Bias Configuration Voltage between drain-to-source, V DS V DD – I D R D – V DS – I S R S = 0 Since I S = I D V DD – I D R D – V DS – I D R S = 0 V DS = V DD – I D (R D + R S ) OR V DS = V D – V S V S = I S R S and V D = V DD – I D R D Voltage between gate-to-source, V GS V GS = V G – V S ; Since V G = 0 V GS = -V S and V S = I S RS Then V GS = - I S R S Fig. 7.9 DC analysis of the self-bias configuration.

35 The value of R S needed to establish the computed V GS can be determined by the previously discussed relationship below. R S = | V GS /I D | The value of R D needed can be determined by taking half of V DD and dividing it by I D. R D = (V DD /2)/I D JFET Biasing, Self- Bias Configuration

36 Remember the purpose of biasing is to set a point of operation (Q- point). In a self-biasing type JFET circuit the Q-point is determined by the given parameters of the JFET itself and values of R S and R D. Setting it at midpoint on the drain curve is most common. One thing not mentioned in the discussion was R G. It’s value is arbitrary but it should be large enough to keep the input resistance high. JFET Biasing, Self- Bias Configuration

37 JFET Biasing, Voltage-Divider Configuration The basic construction exactly the same with BJT, but the dc analysis quite different with I G = 0 for FET The voltage at source, V S must be more positive than the voltage at the gate, V G in order to keep gate- source junction reverse-biased.

38 JFET Biasing, Voltage-Divider Configuration V S = I D R S Gate-to-source voltage; V GS = V G – V S And source voltage is V S = V G – V GS The drain current can be expressed as Gate-to-source analysis

39 JFET Biasing, Voltage-Divider Configuration Drain-to-source analysis V DS = V DD – I D (R D + R S ) V D = V DD – I D R D V S = I D R S