1. JUNCTION FIELD EFFECT TRANSISTOR(JFET)

2. JFET operation can be compared to a water faucet :
The source of water pressure – accumulated electrons at the negative pole of the applied voltage from Drain to Source
The drain of water – electron deficiency (or holes) at the positive pole of the applied voltage from Drain to Source.
The control of flow of water – Gate voltage that controls the width of the n-channel, which in turn controls the flow of electrons in the n-channel from source to drain.

3. JFETs and Their Characteristics
Fig. (a) is the schematic symbol for the n-channel JFET, and Fig. (b) shows the symbol for the p-channel JFET.
The only difference is the direction of the arrow on the gate lead.
Fig. (a)
Fig. (b)

4. JFETs and Their Characteristics
N-Channel
P-Channel

5. Transfer Characteristics
The transfer characteristic of input-to-output is not as straight forward in a JFET as it was in a BJT.
In a BJT,  indicated the relationship between IB (input) and IC (output).
In a JFET, the relationship of VGS (input) and ID (output) is a little more complicated:

6. Transfer Characteristics
From this graph it is easy to determine the value of ID for a given value of VGS.

7. Plotting the Transfer Curve
Shockley’s Equation Methods.
Using IDSS and Vp (VGS(off)) values found in a specification sheet, the Transfer Curve can be plotted using these 3 steps:
Step 1:
Solving for VGS = 0V:
Step 2:
Solving for VGS = Vp (VGS(off)):
Step 3:
Solving for VGS = 0V to Vp:

8. Plotting the Transfer Curve
Shorthand method
VGS ID
IDSS
0.3VP
IDSS/2
0.5
IDSS/4 VP
0mA

9. JFET Symbols

10. VGS Controls ID Basic Operation Characteristics And Parameters
Pinch-Off Voltage
VGS Controls ID
Cutoff Voltage
JFET Transfer Characteristic
JFET Forward Transconductance
Input Resistance and Capacitance
Drain-to-Source Resistance

11. JFET BIASING Self-Bias Voltage-Divider Bias Fixed– Bias
Setting the Q-Point of a Self-Biased JFET
Midpoint Bias
Graphical Analysis of a Self-Biased JFET
Voltage-Divider Bias
Graphical Analysis of a JFET with Voltage-Divider Bias
Q-Point Stability

12. The Drain Characteristic Curve when VGS = 0 VB C
Ohmic
region
Constant-current region
Breakdown
IDSS ID
VDS
Vp (pinch-off voltage)
VGS = 0

13. A Biased n-channel JFET

15. VGS = 0V and VDS = 0V

16. VGS = 0V and VDS = 2V

17. VGS = 0V and VDS = 5V

18. VGS = 0V and VDS = 10V

19. VGS = -0.5V and VDS = 0V

20. VGS = -0.5V and VDS = 2V

21. VGS = -0.5V and VDS = 4V

22. VGS = -0.5V and VDS = 10V

23. VGS = -1V and VDS = 0V

24. VGS = -1V and VDS = 2V

25. VGS = -1V and VDS = 3V

26. VGS = -1V and VDS = 10V

27. VGS = -2V and VDS = 0V

28. VGS = -2V and VDS = 2V

29. VGS = -2V and VDS = 3V

30. VGS = -2V and VDS = 10V

31. IDSS is Drain to Source current with gate Shorted.
VGS(off) is the value of VGS that makes ID approximately zero is the cutoff voltage.
Vp, pinch-off voltage, is the value of VDS at which ID becomes constant .
VGS(off) and Vp are always equal in magnitude but opposite in sign.

32. VGS(off) = - 4 and IDSS = 12mA
Determine the minimum value of VDD to put the device in the constant current region operation.

33. VGS(off) = - 4 and IDSS = 12mA
Determine the minimum value of VDD to put the device in the constant current region operation.
Since VGS(off) = - 4V, Vp = 4V.
VDS = Vp=4V, VGS = 0 V
ID = IDSS = 12 mA
VRD = IDRD =(12mA)(560 Ohm) = 6.72 V
VDD = VDS + DRD = 4 V V = 10.7 V

34. Example of An n-channel JFET transfer characteristic curve

35. Questions VGS(off) = - 8 V and IDSS = 9 mA
Determine the drain current, ID for VGS = 0 V, VGS = - 1 V, and VGS = -4 V
using this formula

36. Answers ID = IDSS (1 - ( VGS/VGS(off)) )^2 For VGS = 0 V
ID = 9 mA (1 - ( 0/-8) )^2 = 9 mA
For VGS = -1 V
ID = 9 mA (1 - ( -1/-8) )^2 = mA
For VGS = -4 V
ID = 9 mA (1 - ( -4/-8) )^2 = mA

37. JFET Forward Transconductance

38. Transconductance formulas
gm0 = (2Idss/( |Vgs(off)| ))
gm = gm0 (1-Vgs/ Vgs(off))
Unit for transconductance, gm, is siemens (S)

39. Fixed-Bias Investigating the input loop IG=0A, therefore VRG=IGRG=0V
Applying KVL for the input loop,
-VGG-VGS=0
VGG= -VGS
It is called fixed-bias configuration due to VGG is a fixed power supply so VGS is fixed
The resulting current,

40. Investigating the graphical approach. Using below tables, we
can draw the graph
VGS ID
IDSS
0.3VP
IDSS/2
0.5
IDSS/4 VP
0mA

41. The fixed level of VGS has been superimposed as a vertical line at
At any point on the vertical line, the level of VG is -VGG--- the level of ID must simply be determined on this vertical line.
The point where the two curves intersect is the common solution to the configuration – commonly referrers to as the quiescent or operating point.
The quiescent level of ID is determine by drawing a horizontal line from the Q-point to the vertical ID axis.

42. Output loop

43. Determine VGSQ, IDQ, VDS, VD, VG, VS

45. Exercise
Determine IDQ, VGSQ, VDS, VD, VG and VS

46. Self Bias
The self-bias configuration eliminates the need for two dc supplies.
The controlling VGS is now determined by the voltage across the resistor RS

47. For the indicated input loop: Mathematical approach:
rearrange and solve.

48. Graphical approach
Draw the device transfer characteristic
Draw the network load line
Use to draw straight line.
First point,
Second point, any point from ID = 0 to ID = IDSS. Choose
the quiescent point obtained at the intersection of the straight line plot and the device characteristic curve.
The quiescent value for ID and VGS can then be determined and used to find the other quantities of interest.

50. For output loop
Apply KVL of output loop
Use ID = IS

52. Determine VGSQ, IDQ,VDS,VS,VG and VD.

54. Example
Determine VGSQ, IDQ, VD,VG,VS and VDS.

56. Voltage-Divider Bias
The source VDD was separated into two equivalent sources to permit a further separation of the input and output regions of the network.
IG = 0A ,Kirchoff’s current law requires that IR1= IR2 and the series equivalent circuit appearing to the left of the figure can be used to find the level of VG.

57. Voltage-Divider Bias VG can be found using the voltage divider rule :
Using Kirchoff’s Law on the input loop:
Rearranging and using ID =IS:
Again the Q point needs to be established by plotting a line that intersects the transfer curve.

58. Procedures for plotting
1. Plot the line: By plotting two points: VGS = VG, ID =0 and VGS = 0, ID = VG/RS
2. Plot the transfer curve by plotting IDSS, VP and calculated values of ID.
3. Where the line intersects the transfer curve is the Q point for the circuit.

59. Once the quiescent values of IDQ and VGSQ are determined, the remaining network analysis can be found.
Output loop:

60. Effect of increasing values of RS

61. Example
Determine IDQ, VGSQ, VD, VS, VDS and VDG.

63. Example
Determine IDQ, VGSQ, VDS, VD and VS

65. Find VDS and VGS when ID = 5mA

66. Vs = ID * RS = (5mA)*(470)
= 2.35 V
VD = VDD – ID * RD
= 15 V – (5mA)(1k)
= 15 V – 5 V = 10 V
VDS = VD – VS
= 10 V – 2.35 V
= 7.65 V
VGS = VG – VS = 0 V – 2.35 V = V

67. Questions RD = 860 Ohm RS = 390 Ohm VDD = 12 V
Find VDS and VGS when ID=8mA
RD = 860 Ohm
RS = 390 Ohm
VDD = 12 V

68. Vs = ID * RS = (8mA)*(390) = 3.12 V VD = VDD – ID * RD
RD = 860 Ohm, RS = 390 Ohm, VDD = 12 V, ID=8mA
Vs = ID * RS = (8mA)*(390)
= 3.12 V
VD = VDD – ID * RD
= 12 V – (8mA)(860 )
= 12 V – 6.88 V = 5.12 V
VDS = VD – VS
= 5.12 V – 3.12 V
= 2 V
VGS = VG – VS = 0 V – 3.12 V = V

69. Setting the Q-Point of a Self-Biased JFET
To determine ID for a desired value of VGS or vice versa.
Rs = | VGS/ID |

70. Midpoint Bias
When VGS = VGS(off)/3.4
ID = IDSS/2
using formula below

71. Graphical Analysis of a Self-Biased JFET
Using VGS = -ID*Rs to:
1) Calculate VGS when ID = 0 (VGS,0)
2) Calculate VGS when ID = IDSS (VGS, IDSS) or
Get IDSS from data sheet
3) Draw a line between (0,0) and (VGS, IDSS)
4) The line intersects the transfer characteristic curve is the Q-point of the Circuit

72. Load Line Calculation 1) Calculate VGS when ID = 0 (VGS,0)
VGS = -ID*RS = - 0*470 = (0,0)
2) Calculate VGS when ID = IDSS (VGS, IDSS) or
Get IDSS from data sheet
VGS = -ID*RS = -10mA*470 = -4.7 V (-4.7,10)
3) Draw a line between (0,0) and (-4.7,10m)
4) The line intersects the transfer characteristic curve is the Q-point of the Circuit.

73. A self Bias dc load line and the Q-point

74. Determine the Q-point for this figure when IDSS = 4 mA

75. 1) Calculate VGS when ID = 0 (VGS,0)
VGS = -ID*RS = - 0*680 = 0
2) Calculate VGS when ID = IDSS (VGS, IDSS) or
Get IDSS from data sheet
VGS = -ID*RS = - 4 mA* 680 Ohms = V
3) Draw a line between (0,0) and (-2.72 V, 4mA)

77. Voltage-Divider Bias IS = ID VG = (R2/(R1+R2)) * VDD
ID = (VG – VGS)/RS

78. Exercise Determine ID and VGS when VD = 7V, Vdd = 12 V R1 = 6.8M Ohms
RD = 3.3 k Ohms
RS = 1.8 k Ohms

79. Answers VG = (R2/(R1+R2)) VDD = (1M / 7.8M)12V = 1.54V
ID = (VDD – VD)/RD = (12 V – 7 V)/3.3k = 1.52mA
VS = IDRS = (1.52mA)(1.8K) = 2.74V
VG = (R2/(R1+R2)) VDD = (1M / 7.8M)12V = 1.54V

80. Graphical Analysis of JFET with Voltage-Divider Bias
For Id = 0
Vs = Id*Rs = (0)*Rs = 0
Vgs = Vg-Vs = Vg – 0V = Vg
For Vgs = 0
Id = (Vg – Vgs)/Rs = Vg/Rs

81. For Id = 0
Vgs = Vg
For Vgs = 0
Id = Vg/Rs

86. Exercise #8
In a certain FET circuit, Vgs = 0V, Vdd = 15 V, Idss = 15 mA, and Rd = 470 ohms. If Rd is decrease to 330 ohms, Idss is.
A) 19.5 mA
B) 10.5 mA
C) 15 mA
D) 1 mA

87. Exercise #8 Answer
In a certain FET circuit, Vgs = 0V, Vdd = 15 V, Idss = 15 mA, and Rd = 470 ohms. If Rd is decrease to 330 ohms, Idss is.
15 mA

88. Exercise #9
The JFET has Vgs(off) = -4 V.
Figure 8-57

89. Exercise #10
Determine the value of Rs required for a self-biased JFET to produce a Vgs for -4 V when Id = 5 mA.