1. ELECTRONICS AND SOLID STATE DEVICES-II
Semester-6

2. JFET

3. Schematic symbol of JFET
Structure and working of JFET
A field effect transistor is a voltage controlled device i.e. the output characteristics of the device are controlled by input voltage.
JFET consists of a p-type or n-type silicon bar containing two pn junctions at the sides as shown in fig.1.
Schematic symbol of JFET

4. JFET POLARITIES
Fig.2 (i) shows the n-channel JFET polarities and fig.2 (ii) shows the p-channel JFET polarities.

5. JFET POLARITIES The following points may be noted:
The input circuit ( i.e. gate to source) of a JFET is reverse biased. This means that the device has high input impedance.
The drain is so biased w.r.t. source that drain current ID flows from the source to drain.
In all JFETs, source current IS is equal to the drain current i.e IS = ID.

6. WORKING OF JEFT Case-i: VDS =0V
When a voltage VDS is applied between drain and source terminals and voltage on the gate is zero as shown in fig.3(i), the two pn junctions at the sides of the bar establish depletion layers.
The electrons will flow from source to drain through a channel between the depletion layers.
The size of the depletion layers determines the width of the channel and hence current conduction through the bar.

7. WORKING OF JEFT Case-ii: VGS is -ve
When a reverse voltage VGS is applied between gate and source terminals, as shown in fig.3(ii),  the width of depletion layer is increased.
This reduces the width of conducting channel, thereby increasing the resistance of n-type bar.
Consequently, the current from source to drain is decreased.
On the other hand, when the reverse bias on the gate is decreased, the width of the depletion layer also decreases.
This increases the width of the conducting channel and hence source to drain current.

8. CHARACTERISTICS OF JFET
There are two types of static characteristics viz
(1) Output or drain characteristic and
(2) Transfer characteristic.
1. Output or Drain Characteristic.
The curve drawn between drain current Ip and drain-source voltage VDS with gate-to source voltage VGS as the parameter is called the drain or output characteristic.

9. DRAIN CHARACTERISTICS OF JFET

10. DRAIN CHARACTERISTICS OF JFET
The Regions that make up a transconductance curve are the following:
Cutoff Region- This is the region where the JFET transistor is off, meaning no
drain current, ID flows from drain to source.
Ohmic Region- This is the region where the JFET transistor begins to show some
resistance to the drain current, ID that is beginning to flow from dain to source.
In this region, response is linear.
Saturation Region- This is the region where the JFET transistor is fully operation and maximum current, for the voltage, VGS that is supplied is flowing. In this region JFET is on and active.
Breakdown Region- This is the region where the voltage, VDD that is supplied to the drain of the transistor exceeds the necessary maximum. At this point, the JFET loses its ability to resist current because too much voltage is applied across its drain-source terminals. The transistor breaks down and current flows from drain to source.

11. PINCH-OFF VOLTAGE
Pinch off voltage is the drain to source voltage after which the drain to source current becomes almost constant and JFET enters into saturation region
In actuality, the term pinch-off is a misnomer in that it suggests the current ID is pinched off and drops to 0 A, however, this is hardly the case— ID maintains a saturation level defined as IDSS.

12. SCHOKLEY’S EQUATION ID : Drain current
IDSS : maximum drain current for a JFET and is defined by the conditions VGS 0 V and VDS > |VP|.
VGS : Gate to source voltage
VP : Pinch off voltage

13. TRANSFER CHARACTERISTICS OF JFET

14. Graphical determination of gm
TRANSCONDUCTANCE
The relationship of a change in ID to the corresponding change in VGS is called transconductance. It is denoted gm and given by:
Graphical determination of gm

15. Mathematical Definitions of gm
Where VGS =0V
Where

16. FET AC EQUIVALENT CIRCUIT

17. JFET BIASING Common source (CS)- Fixed Bias Circuit
The input is on the gate and the output is on the drain
There is a 180 phase shift between input and output

19. Common-Source (CS) Self-Bias Circuit
This is a common-source amplifier configuration, so the input is on the gate and the output is on the drain
There is a 180 phase shift between input and output

20. Calculations
Input impedance:
Output impedance:
Voltage gain: 20

21. Common-Source (CS) Voltage-Divider Bias
This is a common-source amplifier configuration, so the input is on the gate and the output is on the drain. 21

22. Impedances
Input impedance:
Output impedance:
Voltage gain: 22

23. Source Follower (Common-Drain) Circuit
In a common-drain amplifier configuration, the input is on the gate, but the output is from the source.
There is no phase shift between input and output. 23

24. Impedances
Input impedance:
Output impedance:
Voltage gain: 24

25. Common-Gate (CG) Circuit
The input is on the source and the output is on the drain.
There is no phase shift between input and output. 25

26. Calculations
Input impedance:
Output impedance:
Voltage gain: 26