1. 9
Transistor Fundamentals

2. Figure 9.1 Controlled-source models of linear amplifier transistor operation
(a) Current-controlled current source
(b) Voltage-controlled voltage source
(d) Current-controlled voltage source
(c) Voltage-controlled current source v + _ r o

3. Figure 9.2 Models of ideal transistor switchesin
Voltage-controlled switch
Current-controlled switch v + _ r

4. Figure 9.4 Bipolar junction transistors
Collector
Base
Emitter
Circuit symbols B E C
pnp
transistor p + n
npn

5. Figure 9.10 Determination of the operation region of a BJT
40 k E C V CC 1 k
500 BB 12 2 3 4

6. Figure 9.12 A simplified bias circuit for a BJT amplifierBB E C V BE + _ CC CE R
By appropriate choice of ,
and
, the desired Q
point may
be selected.

7. Figure 9.13 Load-line analysis of a simplified BJT amplifier1 2 3 4 5 6 7 8
Collector-emitter voltage, V 9 10 11 12 13 14 15 I B
= 250 A Q
= 200
= 150
= 100
= 50
5 m
10 m
15 m
20 m
25 m
30 m
35 m
40 m
45 m
50 m
Collector current, A

8. Figure 9.15 Circuit illustrating the amplification effect in a BJT+ V BB E C CC R _ ~ – CE BE

9. Figure 9.16 Amplification of sinusoidal oscillations in a BJT50 5 10 15 V CE
(V) I C
(mA) B =
230 A
190
150 t 75 Q
28.6
15.3
110 22

10. Figure 9.20 Practical BJT self-bias DC circuit1 2 C E V CC I B CE – + BE

11. Figure 9.21 DC self-bias circuit represented in equivalent-circuit formCC R 1 2 E C BB I CE _ + BE B
(a)
(b)

12. Figure 9.22 npn BJT large-signal model
= 0 C E
CEO V BE = CE
Cutoff state conditions:
Active state conditions:
sat
Saturated state conditions: + –

13. Figure 9.30(a) An n-channel MOSFET is normally off in the absence of an external electric field
Source
Bulk (substrate)
Drain
Gate n + p D i V DS DD G S _

14. Figure 9.30(d) If the drain and gate supply voltages are both varied a family of curves (shown in Figure 9.31(b)) can be generated, illustrating the MOSFET cutoff, ohmic, saturation, and breakdown regions D i V DS GS DD G S _ + GG

15. Figure 9.32 n-channel enhancement MOSFET circuit and drain characteristic for Example 9.8
(mA) v GS
= 2.8 V
2.6 V
2.4 V
2.2 V
2.0 V
1.8 V
1.6 V
1.4 V DS
(V)
100 80 60 40 20 2 4 6 8 10 V GG ON R G S + – Q

16. Source Drain Gate n Channel p
Figure 9.40(a) When the gate-source voltage is lower than -Vp, no current flows. This is the cutoff region
Source
Drain
Gate n
Channel p

17. Source Drain depletion regions Gate n Channel p
Figure 9.40(b) For small values of drain-source voltage, depletion regions form around the gate sections. As the gate voltage is increased, the depletion regions widen, and the channel width (i.e., the resistance) is controlled by the gate-source voltage. This is the ohmic region of the JFET
Source
Drain
depletion
regions
Gate n
Channel p

18. Source Drain Pinched-off channel Gate n Channel p
Figure 9.40(c) As the drain-source voltage is increased, the depletion regions further widen near the drain end, eventually pinching off the channel. This corresponds to the saturation region
Source
Drain
Pinched-off
channel
Gate n
Channel p

19. Figure 9.41 JFET characteristic curves
1.0
2.0
3.0
4.0
5.0
Drain-source voltage, V
6.0
7.0
8.0
9.0
10.0
800 u
2 m
3 m
4 m
0 V –
0.5 V
1.0 V
1.5 V
2.0 V
2.5 V V GS =
3 V
Drain Current, A