1. Chapter 6 Field Effect Transistors (FETs) By: Muhamad Sani Bin Mustafa

2. Objectives
Explain the operation and characteristics of junction field effect transistors (JFET).
Understand JFET parameters
Discuss and analyze how JFETs are biased
Explain the operation and characteristics of metal oxide semiconductor field effect transistors (MOSFET)
Discuss and analyze how MOSFET are biased
Troubleshoot FET circuits.

3. Introduction
Field effect transistors controls current by voltage applied to the gate. The FET’s major advantage over the BJT is high input resistance. Overall the purpose of the FET is the same as the BJT.

4. The JFET
The junction field effect transistor, like a BJT, controls current flow. The difference is the way this is accomplished. The JFET uses voltage to control the current flow. As you will recall the transistor uses current flow through the base-emitter junction to control current. JFETs can be used as an amplifier just like the BJT.
Fig 7-10 basic JFET circuit
VGG voltage levels control current flow in theVDD, RD circuit.

5. The JFET The terminals of a JFET are the source, gate, and drain.
A JFET can be either p channel or n channel.
Fig 7-1 simplified & 7-4 schem. symbol

6. The JFET
The current is controlled by a field that is developed by the reverse biased gate-source junction (gate is connected to both sides). With more VGG (reverse bias) the field (in white) grows larger. This field or resistance limits the amount of current flow through RD. With low or no VGG current flow is at maximum.
Fig 7-2a JFET fwd biased
please label terminals

7. JFET Characteristics and Parameters
Let’s first take a look at the effects with a VGS of 0V. ID increases proportionally with increases of VDD (VDS increases as VDD is increased). This is called the ohmic region (point A to B).
Reverse-bias between Gate-Drain = Increasing resistance
Fig 7-5a & b JFET circ. & drain curve

8. JFET Characteristics and Parameters
The point when ID ceases to increase regardless of VDD increases is called the pinch-off voltage (point B). This current is called maximum drain current (IDSS). Breakdown (point C) is reached when too much voltage is applied. This of course undesirable, so JFETs operation is always well below this value.
DSS = Drain-to-Source current when gate Shorted
Fig 7-5a & b JFET circ. & drain curve

9. JFET Characteristics and Parameters
Fig 7-5a & b JFET circ. & drain curve

10. JFET Characteristics and Parameters
From this set of curves you can see with increased voltage applied to the gate the ID is limited and of course the pinch-off voltage is lowered as well.
Fig. 7-7a & b JFET circuit & curves

11. JFET Characteristics and Parameters
Fig. 7-7a & b JFET circuit & curves

12. JFET Characteristics and Parameters
We know that as VGS is increased ID will decrease. The point that ID ceases increase is called cutoff. The amount of VGS required to do this is called the cutoff voltage (VGS(off ) ). The field (in white) grows such that it allows practically no current to flow through.
Fig 7-9 JFET cutoff
It is interesting to note that pinch-off voltage (Vp) and cutoff voltage (VGS(off)) are both the same value only opposite polarity.

13. JFET Characteristics and Parameters
The transfer characteristic curve illustrates the control VGS has on ID from cutoff (V GS(off) ) to pinchoff (VP). Note the parabolic shape. The formula below can be used to determine drain current. ID = IDSS(1 - VGS/VGS(off))2
Fig 7-13 transfer curve

14. JFET Characteristics and Parameters
Forward transfer conductance of JFETs is sometimes considered. It is the changes in ID based on changes in VGS.
Input resistance for a JFET is high since the gate -source junction is reverse biased, however the capacitive effects can offset this advantage particularly at high frequencies.
Drain-to-source resistance is the ratio of changes of VDS to ID.

15. Transconductance Forward transfer conductance referred to as
gm = ∆ID /∆VGS.
The value is larger at the top of the curve but becaome smaller as you increase VGS.
At VGS =0, the parameter is known as gmo and can be calculated using this equation:
gmo = 2IDSS/|VGS(off)| and gm = gmo(1-VGS/VGS(off))

16. Transconductance
gmo can be read from the datasheet as gfs or yfs and sometimes written as Forward Transfer Admittance.
gmo = 2IDSS/|VGS(off)| and
gm = gmo(1-VGS/VGS(off))

17. JFET Input Resistance
Since JFET is reverse-biased for operation, its input resistance becomes so large. This is an advantage of using JFET. Looking at the datasheet, you may calculate the resistance value by using the Gate Reverse Current IGSS.
This internal input resistance can be calculated at different VGS voltages as:
RIN=|VGS/IGSS|
As IGSS increases with temperature, RIN will decrease in hotter environment as the JFET is heated.

18. JFET Input Resistance Calculate RIN if IGSS=-2nA and VGS=-20V
RIN=|VGS/IGSS|=|-20/-2n|=10G

19. JFET Biasing
Just as we learned that the bi-polar junction transistor must be biased for proper operation, the JFET too must be biased for operation. Let’s look at some of the methods for biasing JFETs. In most cases the ideal Q-point will be the middle of the transfer characteristic curve which is about half of the IDSS.

20. Normal Biasing

21. JFET Biasing
Self-bias is the most common type of biasing method for JFETs. Notice there is no voltage applied to the gate. The voltage to ground from here will always be 0V. However, the voltage from gate to source (VGS) will be negative for n channel and positive for p channel keeping the junction reverse biased. This voltage can be determined by the formulas below. ID = IS for all JFET circuits.
(n channel) VGS = 0-IDRS
(p channel) VGS = 0-(-IDRS )
Fig 7-16 n channel

22. JFET Biasing

23. ID = IDSS(1 - VGS/VGS(off))2
JFET Biasing
Setting the Q-point requires us to determine a value of RS that will give us the desired ID and VGS.. The formula below shows the relationship.
RS = | VGS/ID |
To be able to do that we must first determine the VGS and ID from the either the transfer characteristic curve or more practically from the formula below. The data sheet provides the IDSS and VGS(off). VGS is the desired voltage to set the bias.
ID = IDSS(1 - VGS/VGS(off))2
Fig. 7-16a n channel JFET
Fig 7-12

24. JFET Biasing
Since midpoint biasing is most common let’s determine how this is done. The values of RS and RD determine the approximate midpoint bias. Half of IDSS would be ID that is midpoint. The VGS to establish this can be determined by the formula below.
VGS  VGS(off)/3.4
Fig. 7-16a n channel JFET
Fig 7-12 n channel curve

25. JFET Biasing
The value of RS needed to establish the computed VGS can be determined by the previously discussed relationship below.
RS = | VGS/ID |
The value of RD needed can be determined by taking half of VDD and dividing it by ID.
RD = (VDD/2)/ID
Fig. 7-16a n channel JFET
Fig 7-12 n channel curve

26. JFET Biasing
Remember the purpose of biasing is to set a point of operation (Q-point). In a self-biasing type JFET circuit the Q-point is determined by the given parameters of the JFET itself and values of RS and RD. Setting it at midpoint on the drain curve is most common.
One thing not mentioned in the discussion was RG. It’s value is arbitrary but it should be large enough to keep the input resistance high.
Fig. 7-16a n channel JFET

27. JFET Biasing
The transfer characteristic curve along with other parameters can be used to determine the mid-point bias Q-point of a self-biased JFET circuit.
First determine the VGS at IDSS from the formula below.
VGS = -IDRS
Where the two lines intersect gives us the ID and VGS (Q-point) needed for mid-point bias. Note that load line extends from VGS(off)(ID= 0A) to VP(ID = IDSS)
Fig 7-21 JFET self bias dc load line
Please try Ex. 8-10

28. JFET Biasing

29. JFET Biasing
Voltage-divider bias can also be used to bias a JFET. R1 and R2 are used to keep the gate-source junction in reverse bias. Operation is no different from self-bias. Determining ID, VGS for a JFET voltage-divider circuit with VD given can be calculated with the formulas below.
ID = VDD - VD/RD
VS = IDRS
VG = (R2/R1 + R2)VDD
VGS = VG - VS
Fig 7-23 n channel voltage divider

30. JFET Biasing
In using the transfer characteristic curve to determine the approximate Q-point we must establish the two points for the load line. The first point is ID = 0 and VGS (note that VGS = VG when ID = 0).
VGS = VG = (R2/R1 + R2)VDD
The second point is ID when VGS is 0.
ID = VG/RS
Fig load line

31. JFET Biasing
Transfer characteristics can vary for JFETs of the same type. This would adversely affect the Q-point. The voltage-divider bias is less affected by this than self-bias. This is an undesirable problem that in extreme cases would require trying several of the same type until you find one that works within the desired range of operation.

32. Experiment: JFET Self Bias Circuit
Transfer characteristics can vary for JFETs of the same type. This would adversely affect the Q-point. The voltage-divider bias is less affected by this than self-bias. This is an undesirable problem that in extreme cases would require trying several of the same type until you find one that works within the desired range of operation.

33. Experiment: JFET Self Bias Circuit
We can use both hand calculations and lab-based measurements to understand the operation of circuits and devices.
For the circuit shown here, we can use equations provided in the lab-manual to analyze the circuit.

34. Experiment: JFET Self Bias Circuit
If we know IDSS, gmo, Rs, RD and VDD, the values of many circuit parameters can easily be calculated.

35. Experiment: JFET Self Bias Circuit
JFET dc gate to source cutoff voltage
= (13.1)
Quiescent dc drain (source) current
ID = (13.2a)
= (13.2b)
Quiescent dc gate to source voltage
VS = IDRS (13.3)
= -VGS that VG=0

36. Experiment: JFET Self Bias Circuit
Quiescent drain voltage
VD = VDD – IDRD (13.4)
Quiescent dc drain to source voltage
VDS = VDD – ID(RD + RS) (13.5)
JFET forward transconductance at Q point
gm = (13.6)

37. The MOSFET
The metal oxide semiconductor field effect transistor (MOSFET) is the second category of FETs. The chief difference is that there no actual pn junction as the p and n materials are insulated from each other. MOSFETs are static sensitive devices and must be handled by appropriate means.
There are depletion MOSFETs (D-MOSFET) and enhancement MOSFETs (E-MOSFET). Note the difference in construction. The E-MOSFET has no structural channel.
Fig 7-29 D-MOSFET construction
Fig 7-32 E-MOSFET construction

38. The MOSFET
The D-MOSFET can be operated in depletion or enhancement modes. To be operated in depletion mode the gate is made more negative effectively narrowing the channel or depleting the channel of electrons.
Fig 7-30a depletion mode
Fig 7-31 DMOSFET schem. symbols

39. The MOSFET
To be operated in the enhancement mode the gate is made more positive, attracting more electrons into the channel for better current flow. Remember we are using n channel MOSFETs for discussion purposes. For p channel MOSFETs, polarities would change.
Fig 7-30b enhancement mode

40. The MOSFET
The E-MOSFET or enhancement MOSFET can operate in only the enhancement mode. With a positive voltage on the gate the p substrate is made more conductive.
Fig 7-32 n channel EMOSFET
Fig 7-33 EMOSFET schem. symbols

41. The MOSFET
The lateral double diffused MOSFET (LDMOSFET) and the V-groove MOSFET (VMOSFET) are specifically designed for high power applications.
Dual gate MOSFETs have two gates which helps control unwanted capacitive effects at high frequencies.
Fig 7-35 and 36 LD and V MOSFETs
Fig 7-38 dual gate schem symbol

42. MOSFET Characteristics and Parameters
Since most of the characteristics and parameters of MOSFETs are the same as JFETs we will cover only the key differences.

43. MOSFET Characteristics and Parameters
For the D-MOSFET we have to also consider it’s enhancement mode. Calculating ID with given parameters in the enhancement mode and depletion mode is the same. Note this equation is no different for ID than JFETs and that the transfer characteristics are similar except for it’s effect in the enhancement mode.
ID = IDSS(1 - VGS/VGS(off) )2
Fig 7-13a & b n & p channel DMOSFET
Remember n and p channel polarity differences.

44. MOSFET Characteristics and Parameters
The E-MOSFET for all practical purposes does not conduct until VGS reaches the threshold voltage (VGS(th)). ID when it is when conducting can be determined by the formulas below. The constant K must first be determined. ID(on) is a data sheet given value.
K = ID(on) /(VGS - VGS(th))2
ID = K(VGS - VGS(th))2
Fig 7-40 a n channel curve

45. MOSFET Biasing
The three ways to bias a MOSFET are zero-bias, voltage-divider bias, and drain-feedback bias.
For D-MOSFET zero biasing as the name implies has no applied bias voltage to the gate. The input voltage swings it into depletion and enhancement mode.
Fig 7-42 a & b zero bias

46. K = ID(on)/(VGS - VGS(th))2
MOSFET Biasing
For E-MOSFETs zero biasing cannot be used. Voltage-divider bias must be used to set the VGS greater than the threshold voltage (VGS(th)). ID can be determined as follows. To determine VGS, normal voltage divider methods can be used. The following formula can now be applied.
K = ID(on)/(VGS - VGS(th))2
ID = K(VGS -VGS(th))2
VDS can be determined by application of Ohm’s law and Kirchhoff’s voltage law to the drain circuit.
Fig 7-44a Voltage-divider EMOSFET

47. MOSFET Biasing
With drain-feedback bias there is no voltage drop across RG making VGS = VDS. With VGS given determining ID can be accomplished by the formula below.
ID = VDD - VDS/RD
Fig 7-44b drain-feedback

48. Troubleshooting
As always, having a thorough knowledge of the devices makes for easier troubleshooting circuits utilizing them. We will discuss some the common faults associated with FET circuits. Experience in troubleshooting is the best teacher having basic theoretical knowledge is extremely helpful.

49. Troubleshooting
If VD = VDD in a self-biased JFET circuit it could be one of several opens. It is a clear indication of no drain current. Use of senses to check for obvious failures the first and easiest step. Replace the FET only if associated components are known to be good.
If VD is less than normal in a self-biased JFET circuit an open in the gate circuit is more than likely the problem. The low drain voltage would be indicative of more drain current flowing than normal.
Fig 7-47a & b self-biased symptoms

50. Troubleshooting
In a zero-biased D-MOSFET or drain-feedback biased E-MOSFET an open in the gate circuit is more difficult to detect. It may seem to be biased properly with dc voltages but will fail to work properly when an ac signal is applied.
Fig 7-48a & b DMOSFET faults

51. Troubleshooting
With a voltage-divider biased E-MOSFET circuit faults are more easily detected. With an open R1 there is no drain current, so the VD = VDD. With an open R2 full VDD is applied to the gate turning it on fully. VD = 0
Fig 7-49 EMOSFET volt.divider faults

52. Summary JFETs are unipolar devices.
JFETs have three terminals: Source, Gate, and Drain.
JFETs have a high input resistance since the gate-source junction is reverse biased.
Unwanted capacitance associated with FETs can be dealt with by using dual gate type FETs.
IDSS for all FETs is the maximum amount of current flow in the drain circuit when VGS is 0V.
All FETs must be biased for proper operation. Midpoint is most common for use in amplifiers.

53. Summary
MOSFETs differ in construction in that the gate is insulated from the channel.
D-MOSFETs can operate in both depletion and enhancement modes. E-MOSFETs can only operate in the enhancement mode.
E-MOSFETs have no physical channel. A channel is induced with VGS greater than VGS(th).
E-MOSFETs have no IDSS parameter.
There are special MOSFET designs for high power applications.