Adaptive Mirror Control System Characterization Presentation Performed by: Boris Goychman & Eyal Tsin Instructor: Tsachi Martsiano Semestrial project, Winter 2012

Project’s Goals Building a system that interface with a PC from one end and control an adaptive mirror on the other end. *Adaptive Mirror – contains 126 capacitors to control the shape of the mirror Learn an approach for practical engineering. Get familiar with FPGA, Logic Design and board design basics.

Project’s Scope Since this is a semestrial project the purpose of this project is to handle and control the data flow PC -> On Board USB Controller -> FPGA -> D2A. There is an option to broaden the project to a second semester and handle the dataflow through other components to the mirror itself.

Challenges Create a system that can work under strict timing limitations – The adaptive mirror updates at 1ms Create an efficient VHDL code Learn and control Phillips USB Controller Learn and control Analog Devices D2A. Write Driver and GUI to the USB Finish the project with 100% percent working system

System Overview

System rates Adaptive mirror – 126 capacitors per 1msec PC to DE2 via USB – up to 12MBps DE2 – 50Mhz Clock Read / Write to / from memory – 1 clock cycle Write time D/A -> Vout = 460ns ( up to 2.17Mhz ) Write / Read time USB -> FPGA = 180ns ( up to 5.55Mhz )

General Data Flow Overview The user will send data over USB using the GUI we will provide. Our FPGA Implementation will control the data arriving through the USB Controller Our FPGA Implementation will send the data and control the D2A The output of the D2A will pass through a DEMUX to a S/H and then to the mirror (not in the scope of our project)

DE2 Philips USB controller Philips USB controller Main State Machine FPGA D/A controller Memory USB controller System Block Diagram GUI USB PC D/A ( DEMUX ) ( Sample and Hold )

System Overview – a more detailed view D/A PC USB DE2 board D/A Controller FPGA Memory Main State machine USB Controller USB

Detailed Data Flow Overview The GUI will provide an interface for the user to send commands via USB The USB Control State Machine will handle the data transfer between the PC and our system The arriving data will be stored in the FPGA internal RAM and if needed will be converted using a LUT inside the FPGA The D2A Control State Machine will handle the outputs from the FPGA to the D2A The Main State Machine will control all our system

Project Components - GUI Mirror Control Center קבל 2 : קבל 3 : קבל 4 : קבל 5 : קבל 6 : קבל 7 : קבל 8 : קבל 9 : קבל 10 : קבל 11 : קבל 12 : קבל 13 : קבל 14 : קבל 15 : קבל 1 : קבל 17 : קבל 16 : SENDRESET

Project Components – USB

Project Components – FPGA

Project Components - D/A

Time-Table (Gantt)

Work Methodology Learn the Datasheet Code VHDL Draw State Machine Code Emulation environment Simulate The code Debug Program The FPGA Documentation On chip Debug