Routability-driven Floorplanning With Buffer Planning Chiu Wing Sham Evangeline F. Y. Young Department of Computer Science & Engineering The Chinese University of Hong Kong

Overview of Presentation Introduction Congestion model Buffer planning Implementation Experimental results Conclusion

Major Role of Floorplanning Minimization of chip area Minimization of interconnect cost Wirelength Timing delay Routability

Our Contributions Improve the routability of the layout by Accurate estimations of congestion at different locations of the packing Consider the positions of the buffer blocks

Buffer Planning Buffer planning is important to circuit design The number of buffer insertions is large and the total size of buffer insertions is significant Buffers cannot be inserted on macro blocks Without planning ahead, buffer locations will be poorly chosen or timing closure cannot be achieved

Design Flow Simulated Annealing Floorplan Evaluation Move a new packing Estimation of congestion Computation of area and wirelength Estimation of buffer usage and buffer resource Netlist and module information of a floorplan A floorplan with optimized area and routability

Design Flow Simulated Annealing Floorplan Evaluation Move a new packing Estimation of congestion Computation of area and wirelength Estimation of buffer usage and buffer resource Netlist and module information of a floorplan A floorplan with optimized area and routability

Traditional Congestion Model The probability that wire k passing through this grid, Prob(x,y,k) =4/6 =0.67

Our Congestion Model Variable interval buffer insertion constraint Adjacent buffers are inserted at distance x  [low, up] from each other for some given low and up Make use of the information of buffer insertions to estimate congestion by probabilistic analysis

Our Congestion Model As the buffers can be inserted in multi-ways: r_success(l) = (P 0 + … + P n )/n, where n is the total number of possible ways for buffer insertions, P 0 … P n are the probabilities of successful buffer insertion for each possible way and r_success(l) is the probability of successful buffer insertion for route l. Assume that up is 3 and low is 2

Our Congestion Model Example: r_success(l) =(P 0 +P 1 +P 2 )/3 =0.413 P 0 = 1.0*1.0 P 1 = 1.0*0.2 P 0 = 1.0*1.0 P 1 = 1.0*0.2 P 2 = 0.2*0.2

Buffer resources, b_prob(x,y) The number of feasible routes pass through each grid for wire k Assume that up is 3 and low is 2 Our Congestion Model The probability that wire k passing through this grid, Prob(x,y,k) =2.00/2.25 =0.89

Our Congestion Model Congestion of the grid (x,y) -Average number of wires passing through the grid (x,y), weight(x,y):

Estimation of the Congestion Compute these Prob(x,y,k) for all co- ordinates x, y and wires k by dynamic programming To compute Prob(x,y,k), we can make use of the Prob(x’,y’,k’)s where (x’,y’)s are closer to the source than (x,y) and the distance between (x’,y’) and (x,y) is within the bound [low, up]

Estimation of Buffer Resources Buffer resources at grid (x,y): where b_space(x,y) is the maximum number of buffer insertions allowed at the grid (x, y) which is related to the amount of empty space in that grid and b_weight(x,y) is the estimated total number of buffer insertions required at the grid (x,y)

Implementation of the Floorplanner Assume variable interval buffer insertion constraint Estimate the wirelength by MST Estimate the amount of buffer resources Evaluate the congestion by probabilistic analysis Apply two phases simulated annealing

Two Phases Simulated Annealing Phase 1 Using simulated annealing Using cost function including area and wirelength only, C1 Phase 2 Using simulated annealing Using cost function including area, wirelength and congestion estimation, C2

Two Phases Simulated Annealing Temperature adjustment Maintain the acceptance rate during the transitional stage by adjusting the temperature Simulated annealing process can be performed smoothly although the cost function is changed Calculating the new temperature, new_T = (new_  C/ old_  C)*old_T

A Simple Global Router The nets are decomposed into two-pin wires A wire is routable if it can be routed from the source to the sink in the shortest Manhattan distance without violating the buffer constraints and the congestion constraints The nets will be routed one after another The routes satisfying the buffer requirement and with the smallest congestion will be chosen

Experimental Results Machine used is Pentium IV 1.2GHz with 512 Mb memory The data sets used are ami33, ami49 and playout Upper bound and lower bound of the variable interval buffer insertion constraint are approximately equal to 2100  m and 4200  m for 0.18  m technology

Experimental Results Compare our two phases routability-driven floorplanner with buffer planning (F1) v.s. the traditional floorplanner (F2): ami33ami49playout F1F1F2F2F1F1F2F2F1F1F2F2 Area Wirelength Congestion Blocked wires Total wires Runtime

Experimental Results Compare our two phases routability-driven floorplanner with buffer planning v.s. the traditional floorplanner: Comparison with original floorplanner ami33ami49playout  Area 0.26 %0.76 %0.19 %  Wirelength %-4.91 %-3.32 %  Congestion % %-5.76 %  Blocked wires % % %  Runtime 5.3x5.2x7.1x

Conclusion A routability-driven floorplanner with buffer planning is implemented The result shows that the floorplan can be less congested and more routable without increasing the area of the floorplan significantly Runtime is affordable when using two phases simulated annealing