1. Fishbone: A Block-Level Placement and Routing Scheme Fan Mo and Robert K. Brayton EECS, UC Berkeley

2. Outline The block level placement and routing problem –Routability, predictability Fishbone scheme –Spine net topology –Base/Virtual pin pair –Row/column routing with left-edge algorithm Integrated placement and routing Experimental results Discussion

3. Block-Level P&R In conventional design flow, the block-level placement and routing are two sequential stages. –During placement, certain net model (fast but inaccurate) is used to estimate wire length, congestion, etc. –During routing, blocks are fixed and nets are routed with certain net model (slow but accurate). Problem occurs when wrong estimation was made during the placement, or even early steps of the routing.

4. RST and HP Rectilinear Steiner Tree (RST) –Smallest wire length –Slowest computation Half-Perimeter Model (HP) –Good estimation of RST –Faster computation –Strictly speaking, HP is not a net topology. It cannot be used to predict congestion and routability A common approach is to use HP in placement and RST in routing.

5. Block-Level Design in Reality Pins of the blocks lie on layer m B. Routing takes place on a couple of higher metal layers, m B+1 and m B+2. Layers m B+1 and m B+2 have preferred routing directions (vertical or horizontal) for better manufacturability. Routability problem may occur, especially in and around pin regions. –Pins of a block may lie close to each other –Pins of adjacent blocks may lie close to each other. –Such routability problems are quite local, which are hard to predict even in the global routing step.

6. The New Routing Scheme We want a net topology and a routing scheme that have –Better predictability of routability than HP (or even RST), especially in and around pin regions. –Faster computation than RST.

7. Spine Topology The output pin of a net is on a vertical wire called "trunk"; and all the input pins connect to the spine by horizontal "branches". –Given pin positions, the net shape is fully determined. –Pin-pin distance is Manhattan. –Routability is easy to detect, given all pin positions.

8. Grids, Columns and Rows The routing grids are given cyclic indices labeled 0,1,2,…, GR-1, where GR is the grid radix. The whole routing space is composed of rows (or columns), each containing grid 0~GR-1.

9. Base Pins GR=6

10. Virtual Pins GR=6 virtual output pin (m B+2 ) trunk virtual input pin (m B+1 ) branch

11. Base/Virtual Pin-Pairs GR=6

12. The Fishbone Routing Given a placement of the blocks, we know the base pin locations (the columns of the base output pins, and the rows of the base input pins). –Only know one coordinate of the virtual pin (Y of virtual output pin and X of virtual input pin). The trunks are assigned to the columns, and the branches are assigned to the rows. Use "left-edge" algorithm to arrange trunks in columns and branches in rows. Then we know the virtual pin positions (points). Overflows in the "left-edge" packing are considered as routing violations. –The Fishbone scheme seeks a placement (and thus the routing) with no violation and some objective function (area and/or delay) minimized.

13. The Integrated Fishbone P&R Simulated-annealing framework. –Sequence-pair –Base/virtual pin and Fishbone routing After a random move (swapping of blocks in the sequence pair, or swapping two I/O ports). –Evaluate area (sequence-pair) –Fishbone routing –Evaluate routing violation, wire length or delay

14. The I/O Ports extended region virtual input pins virtual output pin pseudo branch

15. Experiment Compare the areas, wire lengths and run times of: –Placement and routing with Fishbone. –Placement with RST and Warp Router routing. –Placement with HP and Warp Router routing. –HP placement, post wire length measurement with RST. –Fishbone placement, post wire length measurement with RST. –Fishbone placement, Warp Router routing with base pins. –Fishbone placement, Warp Router routing with virtual pins. Example#Block#I/O#Net#PinGrid radix ami3333421175227 ami4949224079538 playout62192160946569 ibm10030200332799837 ibm101403004340130218 ibm102504005402162089 ibm103605006481194439 ibm1047060076212286410

16. Experimental Results On average, the Fishbone scheme resulted in a 14% area overhead and a 5% increase in wire length. –A price paid for 100% routability and predictability known during placement. Fishbone placement with virtual pins specified (FB ro-v) is 100% routable using the Wrouter. Also it runs much faster (because there are no violations to be repaired). area (mm 2 )average wire length (mm)#routing violations FBHPRSTFB exampleFBHPRSTpl p- RST ro-bro-vplp-RSTroplroro-bro-vHPRST ami335.095.325.100.700.76 0.780.890.900.890.850.832067 ami4959.457.258.93.223.15 3.183.163.24 3.093.120000 playout3492962989.149.429.139.398.929.079.138.918.974042 ibm10073.665.167.27.516.946.976.946.406.766.746.916.906076 ibm10110283.981.08.587.927.937.917.287.687.647.907.8750117 ibm1021271041039.218.438.468.438.118.578.558.878.823013 ibm10315112813110.99.929.939.899.019.509.489.579.5315016 ibm10418715215611.710.5 10.410.611.2 10.2 2302023 compare1.141.0011.051.00 0.981.021.0111.000.7701.061 pl: placed. p-RST: post-placement RST estimation. ro: Wrouter. ro-b: Wrouter. Routing with Fishbone placemen but with base pins only. ro-v: Wrouter. Routing with Fishbone placement and virtual pins.

17. Experimental Results The run time of the Fishbone scheme is the time taken only by the simulated annealing phase, which is on average 80% less than for RST placement; the RST and HP placements need extra time for routing. placement timerouting time FB exampleFBHPRSTro-bro-vHPRST ami331m360m3019m1m140m021m061m15 ami495m071m0554m0m220m020m220m24 playout20m3m151h391m550m131m552n33 ibm10053m8m4h242m401m322m452m52 ibm10172m9m6h023m402m264m274m37 ibm1021h3410m7h076m584m186m067m15 ibm1031h5612m8h099m136m269m0710m ibm1042h1713m9h4213m9m1315m13m compare0.190.0310.910.390.921

18. Discussion Fishbone cannot handle obstructions in the routing layers. No 90 o rotations of the blocks are allowed. Only vertical spine (trunk vertical). Need a pre-defined grid radix GR. Extension to timing-driven version is straightforward. Easy for coupling capacitance extraction.