Presentation on theme: "Analysis of Floorplanning Algorithm in EDA Tools"— Presentation transcript:
1 Analysis of Floorplanning Algorithm in EDA Tools By:RENISHKUMAR V. LADANIM.TECH-2003, DA-IICTGANDHINAGARGUIDE: PROF. ASHOK AMINCO-GUIDE: PROF. AMIT BHATT
2 Floorplanning in context of VLSI physical Design Bottom-up methodologyTop-down methedology:FLOORPLAN-BASED DESIGN METHODOLOGY
3 Floorplanning in context of VLSI physical Design Bottom-up methodologyMay leads to poor utilization of the chip area and excessive wiringTop-down methedology:FLOORPLAN-BASED DESIGN METHODOLOGYIt advocates that layout aspects should be taken into account in all design stages.Advantege:Gives early feed backSuggests valuable architectural modificationsEstimates the whole chip areaEstimates wire lengthEstimates delay and congestion due to wiring
5 Floorplanning Problem Input to the floorplanning problem:A set of blocks, hard of softPin locations of hard blocksA netlist (interconnect pattern)Output expected from the floorplanning problem:Shapes of soft blocksPosition of each blocks in final layoutObjectives:Minimize areaReduce wirelengthsMaximize routability (minimize congestion)Delay of critical pathNoise, heat dissipation, etc.
6 Wire length Estimation The Cost FunctionCost = *Atot + *WtotWhere,Atot = Total area of the packing.Wtot = Total wire length of packing. and = User specified constant.Wire length EstimationExact wire length of each net is not known until routing is done and also pin positions are not known yet for soft blocksTwo ways of wire length estimationcenter-to-center estimationhalf-perimeter estimation
7 Some Constraints in Floorplanning Preplaced constraintBoundary constraintRange constraintNote that in floorplanning some times L-shaped, U-shaped blocks are being considered in addition to rectangular blocks.Floorplan Sizing: A optimization problem in FloorplanningThe availability of flexible blocks implies the possibility of having different shapes for the same hardware units. Its therefore possible to choose a suitable shape for each flexible blocks such that the resulting floorplan is optimal in some sense (e.g. minimal area).
8 Floorplanning Concepts and Approaches to Problem The floorplan problem is known to be NP-completeVarious heuristic approachesSimulated Annealing (SA)Genetic Algorithm (GA)Hybrid approach(SAGA: simulated annealing and genetic algorithm)These algorithms depend on representation of feasible solution spaceClassification of representation:Slicing floorplan representationNon-slicing floorplan representation
9 Slicing StructureRectangular Dissection: Subdivision of a given rectangle by a finite # of horizontal and vertical line segments into a finite # of non-overlapping rectangles.Slicing structure: A rectangular dissection that can be obtained by repetitively subdividing rectangles horizontally or vertically.Slicing tree: A binary tree, where each internal node represents a vertical cut line or horizontal cut line, and each leaf a basic rectangle.Polish expression: Expression obtained Post order traversal of slicing tree. (16+35*2+74+**)Wong and Liu proposed an algorithm based on simulated annealing for slicing floorplan designs using a normalized polish expression(extension of polish expression) to represent a slicing structure.
10 Non-Slicing Structure Not all floorplans are slicingIf the basic rectangles corresponding to leaf nodes in slicing structures can not be obtained by recursive cutting rectangles into smaller rectangles then the floorplan has non-slicing structureNon-Slicing Floorplan RepresentationSequence Pair(SP)Bounded Slicing Grid (BSG)O-treeTransitive Closure Graph (TCG)Corner Block List (CBL)B* TreesGeneralized Polish Expression(GPE)
11 Simulated annealingWell-known high performance optimization technique for combinatorial problems01 Temperature = Intial Temperature;02 Current placement = Random initial placement;03 Current score = Score( Current placement);04 While equilibrium at temperature not reached Do05 Selected component = Select (at random);06 Trail placement = Move (selected component);07 Trail score = Score (trail placement);08 If trail score < current score then09 Current score = trial score;10 Current placement = trail placement;11 else12 if uniform random(0,1) < e-(trail score – current score)/temperature then13 Current score = trial score;14 Current placement = trail placement;15 temperature = temperature * Alpha; // alpha ~ 0.95
12 Comparisons between slicing and non-slicing approach Slicing representationAdvantages:Smaller encoding cost and solution space bringing faster runtime for packingFlexible to deal with hard, preplaced, soft and rectilinear blocksDisadvantages:Optimal solution might not be in the solution space of slicing structureNon-slicing representationOptimal solution might be achieved.Needs more evaluating runtime for packing
13 State-of-art in floorplan representations SPFast-SPBSGO-treeB*-treeCBLTCGGPEIs P-admissible?YesNoNeed sequenceencoding?Constraint graphsfor packing?Solution spacesizen!22n(n+2)O(n!22n-2 /n1.5)O(n!23n-3 /n1.5)O(n!23n-3 /n1.5)N!2-Runtime forpackingO(n2)O(n lg n lg n)O(n)Number of bits todescribe floorplan2n[lg n]2n[lg n]2n+n[lg n]6n+n[lg n]3n+n[lg n]Table 1: Properties of representations. Here, n is the number of modules in the placement.
14 State-of-art in floorplan representations Table 2: Comparisons for runtime and area requirements among O-TREE, B*-TREE, CBL, SP and TCG based on genetic and simulated annealing algorithms. (NA: NOT AVAILABLE)It is important to note that GPE achieves area utilization compared to previous Fast-SP and Enhance O-tree.
15 GPE: Generalized Polish Expression New and easy representation for VLSI floorplanEffectively inherits the useful property of Normalized Polish Expression for slicing structurePresent non-slicing floorplanThe time complexity to transform a GPE to a corresponding placement is O(n).
16 Future planningNote sizing means handling soft(flexible) blocks while floorplanning.Floorplan sizing can be done optimally and efficiently for slicing floorplans“Shape Curve Computation” used for sizing flexible blocksSizing algorithm runs in polynomial timeFloorplan sizing can be done optimally but not efficiently for some slicing non-slicing floorplans, which are using Constraints Graph for packing such as SP, Fast-SP, O-tree and B-tree.GPE a new representation for non-slicing floorplans, which has achieved promising result in area utilization as compared to Fast-SP and O-tree.Since its inherits properties from polish expression for which sizing (shaping for soft blocks) can be done in polynomial time, it raises hopes that with GPE sizing can be done in less time then timing required by sizing for Non slicing floorplans.Study for handling soft(flexible) blocks has been not carried out.