1. Routability-Driven Blockage-Aware Macro Placement Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang

2. outline INTRODUCTION THE PROPOSED ALGORITHM EXPERIMENTAL RESULTS CONCLUSIONS

3. INTRODUCTION A modern system-on-a-chip (SoC) usually hundreds of intellectual property (IP) macros and millions of standard cells. Some of the macros, namely pre-placed macros, need to be placed at specified locations for various concerns, such as power/thermal considerations or the connections with IO pads.

4. INTRODUCTION In macro placement, the pre-placed macros are treated as blockages and not allowed to overlap with other macros or standard cells. For complex designs with many pre-placed macros, therefore, it would make the designs much more difficult.

5. INTRODUCTION The work [10] classifies mixed-size placement algorithms into three types: (1) One-stage mixed-size placement: places macros and standard cells simultaneously (2) Constructive mixed-size placement: places macros constructively (3) Three-stage mixed-size placement: handles the mixed-size placement in three stages, placement prototyping,macro placement,and standard-cell placement

6. INTRODUCTION Three-stage mixed-size placement: handles the mixed-size placement in three stages, placement prototyping,macro placement,and standard-cell placement For the three-stage approach, the MP-tree macro placer has been shown to be packing efficient and easy for implementation for commercial applications.

7. INTRODUCTION

8. Although the MP-tree can pack macros efficiently and robustly, there may still exist vertical overlaps (especially for big macros) because it packs macros along the top and bottom contours. Further, the MP-tree does not model any blockage or pre-placed macro and adopts a shifting method to remove an overlap with a blockage or a pre-placed macro.

9. INTRODUCTION

10. Nevertheless, it might limit the solution space or even fail to get a legal placement, especially when there are a large number of pre- placed or big macros. Therefore, it is desirable to develop a new representation to handle the pre-placed macros and placement blockages which are commonly seen in modern SoC designs.

11. INTRODUCTION We propose a new circularly-packing-tree (CP-tree for short) representation based on MP-tree, which is easy for implementation, fast for operations, and flexible for handling various constraints.

12. As a result, routability plays an essential role for modern circuit placement

13. FLOW

14. PROBLEM FORMULATION

15. THE PROPOSED ALGORITHM An MP-tree consists of a set of packing trees for packing macros to corners and globally optimizes all macros at the same time. To better handle pre-placed macros and remove overlaps between contours, we present the CP-tree with four packing subtrees. There are four types of packing for each packing subtree: L-, T-, R-, and Bpacking packs blocks to the left, top, right, and bottom boundaries of a chip, respectively.

16. CP-tree

17. THE PROPOSED ALGORITHM We further model pre-placed boundary blocks and boundary branches in the CP-tree representation. A pre-placed boundary block represents a macro which is pre-placed along the boundary.

18. PRE-PLACED BOUNDARY BLOCK

19. THE PROPOSED ALGORITHM To place blocks along the chip boundaries circularly, we introduce four boundary branches for a packing subtree to represent the chip boundaries. A boundary branch consists of a set of packing anchors, which are two pseudo terminal nodes and a set of pre-placed boundary nodes, for initialization.

20. BOUNDARY BRANCH

21. For a packing anchor p, it contains the following information: (1) anchor distance : the distance from p to the next packing anchor. (2) the number of branch children : the number of children on the boundary branch between p and the next packing anchor

22. BOUNDARY BRANCH (3) interval space : the rest space after all branch children are placed The value ip of packing anchor p is computed as follows: d p is the anchor distance w c is the width of a branch child c of p

23. BOUNDARY BRANCH (4) anchor width constraint : check whether the interval space is less than 0 or not. (5) switching point : the starting point changing the packing direction for p.

24. BOUNDARY BRANCH

27. CP-tree Floorplan Representation Because any two boundary branches might overlap with each other, we allow the branch blocks with the back-packing direction to shift with the distance Ds.

28. CP-tree Floorplan Representation

29. R-wirelength model To propagate the information of placement prototyping to macro placement, we propose a new routability-aware wirelength model, namely the R-wirelength model. We construct two available layer maps H and V for the respective horizontal and vertical routing directions to record the layer blockages and reflect the routing resource utilization in our R-wirelength model.

30. R-wirelength model The available layer map functions H(b) and V (b) of a bin b can be initialized for the pre-placed macros as follows:

31. R-wirelength model A b is the area of the bin b. L H and L V are the respective numbers of available metal layers for O x (b,m) and O y (b,m) are the overlap functions of a bin b and a preplaced macro m. β H (m) and β V (m) are the layer blockages which define the number of metal layers occupied by the macro m.

32. R-wirelength model

33. Instead of decomposing a net e as twopin nets which is time- consuming, we find a netbox R(e) for the net e to model the half- perimeter wirelength (HPWL) of e. Let Rb(e),Rt(e), Rl(e), Rr(e) be the bottom, top, left, and right of this netbox. Ae be the area of R(e).

34. R-wirelength model we can compute the R-wirelength Wr(e) for the net e as follows:

35. R-wirelength model

36. A smaller R-wirelength implies shorter wirelength and better routability for the placement with macros and standard cells.

37. Simulated Annealing Optimization For the CP-tree representation, we propose a simulated annealing (SA) flow to optimize the macro placement. we use the following five operations to perturb a CP-tree: Op1: rotate a node. Op2: move a node to another place. Op3: swap two nodes. Op4: change the packing direction of a packing anchor. Op5: change the switching point of a packing anchor.

38. Simulated Annealing Optimization With the placement solution, we can evaluate the cost of this solution by a feasibility cost evaluation defined as follows: A is the weighted macro placement area, D is the total macro displacement W is the R-wirelength U is the total number of overlaps between any two macros N is the narrow channel effect

39. Simulated Annealing Optimization The weighted macro placement area is the summation of the area under four contours times a weighted thickness function Θ(c). The weighted thickness function is defined as follows: Tc is thickness of the contour c. Ch and Cw are the height and width of the chip.

40. Simulated Annealing Optimization Here, the thickness of a contour is the maximum height of the contour.

41. Simulated Annealing Optimization A narrow channel, which is formed between two or more macros, usually incurs serious routing congestion. If so, the narrow channel effect can be modeled by P c i /(w c i ・ min(h c i −1, h c i +1)),

42. EXPERIMENTAL RESULTS We conducted experiments based on five real industry benchmarks to evaluate our proposed algorithm. We implemented our algorithm in the C++ programming language on a Linux workstation with 24 Intel Xeon 2.0 GHz CPUs and 72 GB memory. All placement prototypes (global placement results)and standard cell placements were obtained by NTUplace3 [6], and then the final placement results were routed by Cadence SOC Encounter.

43. EXPERIMENTAL RESULTS

44. CONCLUSIONS We have presented a new CP-tree based macro placement algorithm. We have also presented the R-wirelength model to consider routability. Experimental results have shown that our placer can obatin placement solutions with desired routability and wirelength.