1. Merging Synthesis With Layout For Soc Design -- Research Status Jinian Bian and Hongxi Xue Dept. Of Computer Science and Technology, Tsinghua University, Beijing 100084 2002.3.28

2. Contents u The progress status of our work. u Delay-driven algorithm for logic re-synthesis after placement u Interconnect driven high-level synthesis. – Data path synthesis – Control synthesis

3. Progress Status of Our Work u System specification – IIR into HDM Internal Intermediate Representation – C to VHDL : – HDM (IIR) to CDFG FFT.vhdPackageFFT.c

4. Progress Status of Our Work u Interconnect synthesis – Delay-driven post-layout re-synthesis – Interconnect driven high-level synthesis » Data path synthesis combining with floor-planning » Delay driven control synthesis

5. Progress Status of Our Work u HW/SW partitioning – Partition modeling – Partition algorithm » Simulated annealing algorithm » Tabu algorithm » Search space smoothing algorithm – Partition system

6. Interconnect Driven Synthesis u Background – Interconnect wires play the dominating role for circuit performance and area instead of function units.

7. Interconnect Driven Synthesis

8. Traditional Flow

9. Our Approach Hardware Spec. High-Level Synthesis Floor-planning RT-Level Synthesis Logic Synthesis Global Placement Re-Synthesis Incremental PlacementDetail Placement Routing

10. Delay-driven Post-layout Re-synthesis

11. Re-synthesis Logic Synthesis Placement Detail Placement and Routing Re-Synthesis + Incremental Placement

12. Our System Flow

13. Delay Calculation u Using the method in the placement u When get a new gate, allocate it to an ideal position

14. Buffer Insertion A (a) Before buffer insertion B C BC A (b) After buffer insertion

15. Gate Resizing gate_resize() foreach gate g in the circuit{ if (g is non-critical) continue; if (g’s better alternative gate n not exist) continue; replace g with n; re-calculate the delay of the circuit; if (delay is not reduced) recover g; }

16. Alternative Wire a c b a c b

17. Local Logic Substitution u Uses the model mapping method to search for the local alternative circuit

18. Local Logic Substitution a b c d a b c d

19. u The critical path may be shorten, – eg: if the wires marked red are critical path, in the alternative circuit, the path is shorten, but the non-critical path (follows input c) is lengthen a b c d a b c d

20. Experimental Results

21. Result Graph

22. Conclusion u Our system begins with the circuit after the initial placement and performs local re-synthesis to reduce the delay. u A final netlist and placement are then generated after the incremental placement. u The result shows the system is a fine combination of synthesis and physical design. The future work may be replacing the greedy algorithm with the heuristic algorithm.

23. Interconnect Driven High-level Synthesis

24. Behavior Description Entity example is Port( a,b,cin: in bit; S,cout: out bin); End example; Architecture behavior of example is Begin If a=‘1’ and b=‘1’ and cin=‘1’ thens <= ‘1’; Elsif …… …… End;

25. BEHAVIOR DESCRIPTION VHDL Behavior Synthesis Data Path Controller CDFG layout HDM-IIR

26. Problems to Be Solved u How to get information of interconnection delay at higher level? u How to bind floor-planning with high-level synthesis together? u How to achieve an accurate result with limited time?

27. Our Approach CDFG & Restriction Estimate Steps & Resources Make Grids Make CBL Simulate Annealing Result Heuristic AlgorithmSSS Hardware Spec. From HW/SW

28. Representation of Scheduling and Binding Result Using a Two –Dimensional Table u

29. Get a New Solution by Changing the Placement of the Table u Select one operation randomly, changes its column. A B D C E A B C D E

30. u Select one operation randomly u According to the step range of the operation calculated by ASAP and ALAP algorithm, select a new row to place the operation randomly u Adjust the rows of the operations that violate the precedence constraints, finally, decide the columns of these operations. A B D C E A B D C E

31. Corner Block List We use CBL(Corner Block List) to show the result of floorplan. CBL is based-on non-slicing floorplan. 3 4 5 6 1 2 7 Example: Seq=(1234567) L=(010011) T=(10010010) Example: Seq=(1234567) L=(010011) T=(10010010)

32. Corner Block List u The most important thing is – Any (S,L,T) is validate!!! u We can get new floorplan-solution by changing the (S,L,T) group.

33. Controller Synthesis CDFGData Path FSM State Simplification State Assigned placement

34. State Assigned u Various-length state assigned algorithm e.g. 10 states: 4-10 bits, The optimal solution: How many bits? How to encode?

35. Conclusions By binding and floor-planning into a single phase: u We can obtain more accurate information of interconnections in high-level synthesis. u The floor-planning can benefit from the information of scheduling and binding u There are still much work to be done on how to use the information to avoid randomness of the simulated annealing approach.

36. The Future Work u Combine HLS with the result of HW/SW. u Use different algorithms instead of simulated annealing algorithm. – Heuristic algorithms – Search space smoothing – Using re-timing technique

37. Thank You !!!