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CMOS Circuit Design for Minimum Dynamic Power and Highest Speed Tezaswi Raja, Dept. of ECE, Rutgers University Vishwani D. Agrawal, Dept. of ECE, Auburn.

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Presentation on theme: "CMOS Circuit Design for Minimum Dynamic Power and Highest Speed Tezaswi Raja, Dept. of ECE, Rutgers University Vishwani D. Agrawal, Dept. of ECE, Auburn."— Presentation transcript:

1 CMOS Circuit Design for Minimum Dynamic Power and Highest Speed Tezaswi Raja, Dept. of ECE, Rutgers University Vishwani D. Agrawal, Dept. of ECE, Auburn University Michael L. Bushnell, Dept. of ECE, Rutgers University Research Funded by: A National Science Foundation Grant

2 Jan 9, 2004Int'l Conf. on VLSI Design, 20042 Talk Outline Motivation Objective Prior Work New Approach Results Conclusion and Future Work

3 Jan 9, 2004Int'l Conf. on VLSI Design, 20043 Motivation Power consumption due to glitches can exceed 30- 40% of total power consumption. Existing linear programming techniques eliminate glitches, but may insert delay buffers when overall circuit delay is constrained. Delay buffers consume power themselves and thus reduce power saving – also chip area increases. Example: c1355, a 619-gate circuit needed 224 buffers -- 36 % increase in gates – for 42% power saving and no IO delay increase.

4 Jan 9, 2004Int'l Conf. on VLSI Design, 20044 Problem Statement Find a linear program (LP) to determine gate delays in a CMOS circuit such that: All glitches are eliminated No delay buffers are inserted in the circuit Circuit operates at the highest possible speed permitted by the device technology. Note: The objective is to minimize switching power. Hence, no attempt is made to reduce short-circuit and leakage power, which is an order of magnitude lower for present CMOS technologies; those components of power may be addressed in the future research.

5 Jan 9, 2004Int'l Conf. on VLSI Design, 20045 CMOS Power Dissipation Short circuit power Leakage power (I DDQ ) Dynamic power Essential transitions Glitches Each transition dissipates CV 2 /2 Short circuit and leakage power components are at least an order of magnitude lower than the dynamic power in present day technologies. V C

6 Jan 9, 2004Int'l Conf. on VLSI Design, 20046 What Are Glitches? Glitches occur due to differential (unbalanced) path delays. Glitches are transients that are unnecessary for the correct functioning of the circuit. Glitches waste power in CMOS circuits. Delay =1 2 2

7 Jan 9, 2004Int'l Conf. on VLSI Design, 20047 Glitch Suppression Differential Path Delay Path P1 Path P2 Differential Delay = |delay (P1) – delay (P2)|; it is the width of the maximum potential glitch at the gate output. For complete glitch suppression: for each gate, inertial delay > differential delay To satisfy this condition, previous low-power design methods insert delay buffers in the circuit. Power will be further reduced if glitch suppression could be achieved without buffers.

8 Jan 9, 2004Int'l Conf. on VLSI Design, 20048 Example: Why Use Buffers? Delay unit is the smallest delay possible for a gate in a given technology. Critical Path is the longest delay path in the circuit and determines the speed of the circuit. 1 1 1 Critical path delay = 3

9 Jan 9, 2004Int'l Conf. on VLSI Design, 20049 For glitch free operation of first gate: Differential delay at inputs  inertial delay OK 1 1 1 Example (cont.) 0 0 time

10 Jan 9, 2004Int'l Conf. on VLSI Design, 200410 1 1 1 Example (cont.) For glitch free operation of second gate: Differential delay at inputs  inertial delay OK 1 0

11 Jan 9, 2004Int'l Conf. on VLSI Design, 200411 1 1 1 Example (cont.) For glitch free operation of third gate: Differential delay at inputs  inertial delay Not true for gate 3 2 0

12 Jan 9, 2004Int'l Conf. on VLSI Design, 200412 1 1 1 Example (cont.) For glitch free operation with no IO delay increase: Must add a delay buffer. Buffer is necessary for conventional gate design – only gate output delay is controllable. 2 1 1

13 Jan 9, 2004Int'l Conf. on VLSI Design, 200413 1 1 Controllable Input Delay Gates Assume gate input delays to be controllable Glitches can be suppressed without buffers 2 0 1 2

14 Jan 9, 2004Int'l Conf. on VLSI Design, 200414 Delay Model for a New Gate Separate the output (inertial) and input delay components. d 3 - output delay of the gate. d 3,1 - input delay of the gate along path from 1 to 3. Gate design is feasible and is under development... Technology constraint: input delay difference has an upper bound, which we define as Gate Input Differential Delay Upper Bound ( u b ). d 3,1 + d 3 3 1 2 d 3,2 + d 3

15 Jan 9, 2004Int'l Conf. on VLSI Design, 200415 Gate Input Differential Delay Upper Bound (u b ) It is a measure of the maximum difference in delay of any two IO paths through the gate, that can be designed in a given CMOS technology. Arbitrary input delays cannot be realized in practice due to the technology limitation at the transistor and layout levels. The bound u b is the limit of flexibility allowed by the technology to the designer at the transistor and layout levels. The following feasibility condition must be imposed while determining delays for glitch suppression: 0  d i, j  u b

16 Jan 9, 2004Int'l Conf. on VLSI Design, 200416 A New Linear Program Contains following components Variables Gate inertial delay variables (d i ) Input delay variables (d i,j ) Timing window variables Constraints Gate delay constraints Gate input delay upper bound constraints Differential delay constraints Maximum delay constraints Objective function Let us consider a simple example combinational circuit.

17 Jan 9, 2004Int'l Conf. on VLSI Design, 200417 6 New LP Example 5 1 7 2 3 4 Gate inertial delay variables d 5..d 7 Gate input delay variables d i, j for every path through gate i from input j Corresponding window variables t 5..t 7 and T 5..T 7. d 5,1 + d 5 d 7,4 + d 7 d 5,2 + d 5 d 6,2 + d 6 d 6,3 + d 6 d 7,5 + d 7 d 7,6 + d 7

18 Jan 9, 2004Int'l Conf. on VLSI Design, 200418 6 New LP Example (cont.) 5 1 7 2 3 4 d 5,1 + d 5 d 7,4 + d 7 d 5,2 + d 5 d 6,2 + d 6 d 6,3 + d 6 d 7,5 + d 7 d 7,6 + d 7 d 5  1 Inertial delay constraint for gate 5: d 5  1 Input delay constraints for gate 5: 0  d 5,1  u b 0  d 5,1  u b 0  d 5,2  u b 0  d 5,2  u b

19 Jan 9, 2004Int'l Conf. on VLSI Design, 200419 6 New LP Example (cont.) 5 1 7 2 3 4 d 5,1 + d 5 d 7,4 + d 7 d 5,2 + d 5 d 6,2 + d 6 d 6,3 + d 6 d 7,5 + d 7 d 7,6 + d 7 Differential delay constraints for gate 5: T 5 > T 5,1 + d 5 ;t 5 T 5 – t 5 ; T 5 > T 5,2 + d 5 ;t 5 < t 5,2 + d 5 ;

20 Jan 9, 2004Int'l Conf. on VLSI Design, 200420 6 New LP Example (cont.) 5 1 7 2 3 4 d 5,1 + d 5 d 7,4 + d 7 d 5,2 + d 5 d 6,2 + d 6 d 6,3 + d 6 d 7,5 + d 7 d 7,6 + d 7 Differential delay constraints for gate 5: T 5,1 > T 5 + d 5,1 ; T 5,2 > T 5 + d 5,2 ; t 5,1 < t 5 + d 5,1 ; t 5,2 < t 5 + d 5,2 ;

21 Jan 9, 2004Int'l Conf. on VLSI Design, 200421 6 New LP Example (cont.) 5 1 7 2 3 4 d 5,1 + d 5 d 7,4 + d 7 d 5,2 + d 5 d 6,2 + d 6 d 6,3 + d 6 d 7,5 + d 7 d 7,6 + d 7 IO delay constraint for each PO in the circuit: T 7  maxdelay; maxdelay is the parameter which gives the delay of the critical path. This determines the speed of operation of the circuit.

22 Jan 9, 2004Int'l Conf. on VLSI Design, 200422 6 New LP Example (cont.) 5 1 7 2 3 4 d 5,1 + d 5 d 7,4 + d 7 d 5,2 + d 5 d 6,2 + d 6 d 6,3 + d 6 d 7,5 + d 7 d 7,6 + d 7 Objective Function : minimize maxdelay; This gives the fastest and lowest dynamic power consuming circuit, given the feasibility condition for the technology.

23 Jan 9, 2004Int'l Conf. on VLSI Design, 200423 Solution Curves u b =0 u b =5 u b =10 u b =15 u b = ∞ Fastest Possible Design Minimum Dynamic power Maxdelay Power Power consumed by buffers Previous solutions with buffers New solutions

24 Jan 9, 2004Int'l Conf. on VLSI Design, 200424 Results: Procedure Outline C++ Program AMPL Power Estimator Combinational circuit netlist Results Constraint-set Optimized delays

25 Jan 9, 2004Int'l Conf. on VLSI Design, 200425 Results on Feasibility Upper Bound (u b ) Maxdelay is normalized to the fastest possible circuit design. Each curve is a different benchmark circuit. As we increase u b, the circuit becomes faster. Flexibility required for fastest operation of circuit is proportional to the size of the circuit.

26 Jan 9, 2004Int'l Conf. on VLSI Design, 200426 Results: Low-Power Design CircuitUnoptimized power Optimized power No. of vectors maxdelayNorm. delay ubub c4321.00.5256714.175 1.00.4956271.5810 1.00.4856171.0015 c4991.00.7054342.260 1.00.7554151.005 c8801.00.4878451.5010 1.00.4778301.0015 c13551.00.4787712.9510 1.00.4687461.9115

27 Jan 9, 2004Int'l Conf. on VLSI Design, 200427 Comparison with Conventional Gate Design (u b =0) (Raja et al., VLSI Des. `03) Conventional gatesVariable input delay gates CircuitPowermaxdelayBuffersPowermaxdelay ubub c4320.721.0950.481.015 0.622.0660.491.5810 c4990.911.4480.751.0015 0.702.200.702.2610 c8800.681.0620.471.0015 0.682.0340.481.5010 c13550.581.02240.461.0015 0.572.01920.472.0810

28 Jan 9, 2004Int'l Conf. on VLSI Design, 200428Conclusion Main idea: Minimum dynamic power circuits can be designed if gates with variable input delays are used. The new design suppresses all glitches without any delay buffers. Speed of the new design depends on the gate input delay variability allowed by the technology. A linear program solution demonstrates the idea. Results show average power savings up to 52%. Future work: Variable input delay gate design.

29 Jan 9, 2004Int'l Conf. on VLSI Design, 200429 Thank you

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