1 Evaluation and Analysis of Connector Performance for the Spacewire Back Plane Koji Shibuya Keitaro Yamagishi Hideyuki Oh-hashi Seiichi Saito Masaharu.

Slides:

Advertisements

Similar presentations

Suspended Substrates and Their Applications in High Speed Communications By Ron Miller, Consultant, Signal Integrity Design, GHz Data, Newark California.

Advertisements

Practical Radio design

DESIGN CHALLENGES OF AN ADVANCED SPACEWIRE ASSEMBLY FOR HIGH SPEED INTER-UNIT DATA LINK Joachim Mueller, W.L. Gore&Associates

1 Designing for DVI General Applications Considerations.

DCN286 Introduction to Data Communication Technology Session 5.

1 Copyright Pericom Semiconductor 2007 Last Slide PERICOM CONFIDENTIAL INFORMATION SATA&SAS ReDriver Application Guide FAE Training Lingsan Quan Application.

[ 1 ] LVDS links Servizio Elettronico Laboratori Frascati INFN - Laboratori Nazionali di Frascati G. Felici LVDS links.

By Jonathan Coup.  Crosstalk is the transfer of energy between adjacent conductors due to either capacitive or inductive coupling.  In order for crosstalk.

Gigabit Ethernet Group 1 Harsh Sopory Kaushik Narayanan Nafeez Bin Taher.

1CADENCE DESIGN SYSTEMS, INC. Using Allegro PCB SI to Analyze a Board’s Power Delivery System from Power Source to Die Pad International Cadence Usergroup.

1 - David M. Zar - 5/20/2015 CSE464 Coupling Calculations via Odd/Even Modes Spring, 2009 David M. Zar (Based on notes by Fred U. Rosenberger)

CPE495 Computer Engineering Design I Emil Jovanov Electrical and Computer Engineering The University of Alabama in Huntsville Introduction to PCB Design.

Chapter 5 Interconnect RLC Model n Efficient capacitance model Efficient inductance model Efficient inductance model RC and RLC circuit model generation.

Oct-03 ©Cisco Systems CCNA Semester 1 Version 3 Comp11 Mod4 – St. Lawrence College – Cornwall Campus, ON, Canada – Clark slide 1 Cisco Systems CCNA Version.

High speed digital systems Project Status D0913 Avital Katz Elad Yaniv D0913 Avital Katz Elad Yaniv.

Microcomputer Buses Outline –What is a Bus? –Interfaces –Open Collector Buses –Tristate Buses –Bus Contention –Transmission Lines Goal –Understand bus.

Date Conference Paris February 19th 2004 Seite 1 © Copyright PPC ELECTRONIC AG Optical layers PPC Electronic OPTOBOARD ®

RS422, RS485, RS423, RS449 and V.35 Data Communications (E&T2760): RS422, RS485, RS423, RS449 and V.35.

Link A/D converters and Microcontrollers using Long Transmission Lines John WU Precision Analog - Data Converter Applications Engineer

AZIZ112/MAPLD2004 Printed Circuit Board Simulation: A Look at Next Generation Simulation Tools and Their Correlation to Laboratory Measurements Shahana.

Numerical Electromagnetics LN13_High Speed Circuits 1 /10 High-Speed Circuits (1 sessions)

Differential Signals EECS 713 Project by Jay Fuller :) What are they? When to use them Traces, connectors, terminations, etc.

VELO upgrade electronics – HYBRIDS Tony Smith University of Liverpool.

Solderless PCB Launch Connectors

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 38: December 3, 2014 Transmission Lines.

Impact of PCB routing techniques on EMC performance of High Speed Interfaces Presented on: March 13th, 2014.

TDS8000 and TDR Considerations to Help Solve Signal Integrity Issues.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 35: December 5, 2012 Transmission Lines.

10. Transmission Line 서강대학교 전자공학과 윤상원 교수

3M Electronics 3M CONFIDENTIAL © 3M All Rights Reserved. 3M™ MetPak™ HSHM Press-Fit B22 Connector Training Abhay Joshi – Global Product Marketing.

Transmission Lines No. 1  Seattle Pacific University Transmission Lines Kevin Bolding Electrical Engineering Seattle Pacific University.

Light weight readout cable simulations for inner barrel pixel readout

IPC Power Distribution Considerations A predominately important factor that should be considered in the design of a printed board is power distribution.

High Speed Interconnect Solutions HIROSE ELECTRIC IT3-32mm SI Report Three-Piece Mezzanine Connector for 20+ Gbps Applications October 29, 2009.

PCB Traces CK Cheng CSE Dept. UCSD 1. PCB Traces 2.

SpecctraQuest Simulation Winter 2003/4 Final Presentation Date : Student : Kobi Ochayon Supervisor : Boaz Mizrachi.

Questions on IFPAC_SCHEMATIC. Signal Chain Preamplifier Compensation Capacitor should go to –Vs, not GND Where is resistor For compensation Network? Does.

12006 MAPLD International ConferenceSpaceWire 101 Seminar SpaceWire Physical Layer Issues 2006 MAPLD International Conference Washington, D.C. September.

12/4/2002 The Ground Conundrum - Class 20 Assignment: Find and research papers on this subject, be prepared to defend research.

Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 36: December 6, 2010 Transmission Lines.

The Interconnect Modeling Company™ High-Speed Interconnect Measurements and Modeling Dima Smolyansky TDA Systems, Inc.

Example Snapshots From Some Of The Signal Integrity Interactive Software Modules The following slides highlight some of the output graphs/plots from the.

E-Cal Readout Boards - 8 Boards total -Design & Fabrication at Jlab - Assembly at Orsay Nick Nganga HPS Collaboration Oct Jlab.

Global Circuit Page 1  Basic Design Rule for Advanced PCB (1) 1. High speed current path Load Driving gate Current trace At low frequency current, follows.

Impedance Measurements on a PCB

A Compact Inductively Coupled Connector for Mobile Devices Wenxu Zhao, Peter Gadfort, Evan Erickson, Paul D. Franzon North Carolina State University Introduction.

EECS 713 Project Instructor: Prof. Allen Presented by: Chen Jia.

Getting faster bandwidth HervéGrabas Getting faster bandwidth - Hervé Grabas1.

Power Line Communication for Hybrid Power/Signal Pin SOC Design CK Cheng CSE Dept, UC San Diego.

Exam 2 information Open book, open notes, bring a calculator Wednesday Dec 16, 10:30 to 1:00 pm Eligible topics (1 of 3) (not an exhaustive list) Exam.

Chapter 2. High-speed properties of logic gates.

전자파 연구실 1 5. Ground planes and layer stacking. 전자파 연구실 2 Provide stable reference voltages for exchanging digital signals Distribute power to all logic.

High Speed Properties of Digital Gates, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology

Non Ideal Behavior of Components, Copyright F. Canavero, R. Fantino Licensed to HDT - High Design Technology NIB_2 Course outline.

Piero Belforte, HDT 1998: Advanced Simulation and Modeling for Electronic System Hardware Design Part3

Piero Belforte, HDT, July 2000: MERITA Methodology to Evaluate Radiation in Information Technology Application, methodologies and software solutions by Carla Giachino,

Silicon Valley Test Conference 2013

Smith Chart & Matching Anurag Nigam.

Arria 10 External Memory Interface Board Guidelines

High-Speed Serial Link Layout Recommendations –

HPS Motherboard Electronic Design

Open book, open notes, bring a calculator

High-Speed Serial Link Layout Recommendations –

First slides: Prof. Stojanovic, MIT Last slides: Prof. Dally, Stanford

XMBTM Product 10 Gbps Backplane using Multiwire ® Technology

Mini SAS HD Connector Simulation

Microstrips as Transmission Lines

SAS-3 12G Connector Drive Power Pin Configuration

GIGABIT ETHERNET DESIGN ECE Spring 2004

Progress on the 40 MHz SEU Test System based on DE2 Board

Presentation transcript:

1 Evaluation and Analysis of Connector Performance for the Spacewire Back Plane Koji Shibuya Keitaro Yamagishi Hideyuki Oh-hashi Seiichi Saito Masaharu Nomachi International SpaceWire Conference 2008 Nov

2 1.Introduction 2.Connector Evaluation Board 3.Transmission Characteristics Evaluation 4.Crosstalk Evaluation 5.Eye-Pattern Waveform Analysis 6.Conclusion Contents

3 1. Introduction Backplane System Backplane Daughter board Receiver Connector Driver SpaceWire backplane system

4 1. Introduction -Connectors which have been selected by the space qualified are NOT designed for high-speed Signal Transmission purpose. impedance mismatching and crosstalk are generated Evaluation and Analysis of Connector Performance is important. Impedance Mismatch Crosstalk SpaceWire backplane connectors

5 2. Connector Evaluation Board PCB2 (Daughter board) Evaluation system for a backplane connector PCB1 (Backplane) Connector for spacewire backplane - PCB1 corresponds to a backplane. - PCB2 corresponds to a daughter board.

6 2. Connector Evaluation Board Measurement Setup

7 3. Transmission Characteristics Evaluation A B C D E F G H Differential Pairs GND Pins Pin assignment for the transmission characteristics evaluation Edge of daughter board Side view of evaluation board

8 Measurement Results of Return Loss and Insertion Loss Differential return loss (Sdd11)Differential insertion loss (Sdd21) -Differences between different pin assignments become remarkable in frequency range higher than 1GHz. - The pin assignments using the long pins for signals cause characteristic degradation. 3. Transmission Characteristics Evaluation

9 4. Crosstalk Evaluation Differential Pairs (Victim) Aggressive signal pins GND Pins Pin assignment for crosstalk evaluation Static signal pins No GND pins around the victim GND pins existing around the victim a b c d e

10 Measurement Results of Crosstalk No GND pins around the victimGND pins existing around the victim The pin assignment of the GND pins around the differential pair is effective to reduce the crosstalk from the other signal. ( 15dB or more ) Crosstalk can be dramatically reduced by ground pins around victim. 4. Crosstalk Evaluation

11 5. Eye-Pattern Waveform Analysis Waveform Simulation Model  Assuming High Speed Back Plane System - 50 cm total trace Gbps data rate - 2 connectors Differential Transmission Lines Signal Source Received signal  Pin Assignment - E (shortest pin) and H (longest pin) Connector model Connector model Differential Transmission Lines Differential Transmission Lines

12 5. Eye-Pattern Waveform Analysis Pin Assignment E (Short pins) Pin Assignment H (Long pins) Results of Analysis - Eye-Pattern of pin assignments E is better for transmission

13 6. Conclusion 1. The pin assignments using the long pins for signals cause characteristic degradation. 2. The pin assignment of the GND pins around the differential pair is effective to reduce the crosstalk from the other signals. 3. The eye-pattern waveforms were shown by the simulation. the 3Gbps backplane transmission is possible using the connector selected by the space qualified design. The connector selected by the space qualified design can use for the system of over Gbps high speed signal transmission via the backplane by suitable pin assignment design.