1. SAS-3 12G Connector Drive Power Pin Configuration
Ray Pavlak
11-270r0

2. Typical Enterprise Drive Connector Power Layout (Not to Scale)
Traces are ~ 20 mils wide & ~10 mils long
Electronic Fuse IC Area
+12V
Gray copper fill area appears constant among products. Gold traces may attach from center or end as shown.
Capacitor locations may vary as shown across products. Capacitors have their own ground via to ground plane. There may be more than 1 capacitor on each supply. Typical capacitance: 0.01 µF to 22 µF. Typical enterprise products: +5V: 1 µF, +12V: 0.01 µF
Enterprise products have an electronic fuse with a larger amount of bulk capacitance (~ 1 – 22 µF) on the drive side of the fuse. The fuse is a active device which provides hot-plug inrush current limiting while charging this bulk capacitance. A lower value of capacitance on the connector side of the fuse minimizes hot-plug inrush current yet still effectively reduces HF noise.
It is not known what the HF behavior (> 1 GHz) of the fuse is or how it may affect pin impedance or crosstalk, but it is reasonable to assume that the low impedance of the connector-side capacitors may dominate HF behavior.
GND
LED
GND
P15
P14
P13
P12
P11
P10 P9 P8 P7 P6 P5 P4 P3 P2 P1
Electronic Fuse IC Area
+5V
GND
Gray shape is ~ 90 mils wide x 125 to 140 mils tall
+3.3V unused but connected together
Trace width ~ 10 mils
+3.3V

3. Observations Large variation among products
Capacitor values
Layout (copper shapes)
Shapes may have resonances in the frequencies of interest: Impedance to ground may be high or low vs. frequency
+5V and +12V power pins bussed together by a large shape
+3.3V bussed together with thin traces supporting drive detect
Not the same as connecting an impedance to ground per pin (impedances to ground do not connect pins together)
Capacitor(s) provide a varying impedance to ground vs. frequency unlike an ideal resistor

4. Questions
With respect to crosstalk, is the connection of pins together more significant than the absolute impedance to ground?
Can connector vendor simulations decide?
The reported behavior that higher power pin resistances to ground improve crosstalk is not expected. We need to understand why:
Is the pin and trace resonant making it high impedance?
Do all connector modelers agree on this phenomena?
Is something subtle or unanticipated wrong in the model? (e.g., convergence accuracy, boundary reflections, etc.)

5. Thoughts
Assume that pin-to-pin connection is significant for crosstalk
1st Attempt at a definition:
Define a small copper shape with short traces to connect pins (90 x 125 mils? Dielectric thickness?)
Define a small capacitor (~ 0.01 uF) to define high frequency (> 10 MHz) impedance to ground (mounting/ESL significant > 1 GHz)
There are difficulties with defining a “small capacitor” for 3D modeling
Where to put it? (placement sensitivity)
Do we model the entire capacitor pads, traces, and via to ground? (takes more memory and compute resources)
Or define a simple sheet impedance to ground?
What values for ESR and ESL?
Ideal part in model environment (can’t build it for measurement)

6. More Thoughts
Assume that pin-to-pin connection is significant for crosstalk
Assume that pins connected and floating from ground is near worst case or at least a reasonable case
2nd Attempt at a definition (preferred):
Define a small copper shape with short traces to connect pins (90 x 125 mils? Dielectric thickness?)
Do not define a capacitor to ground at all
Trade-offs
Pro:
Easy to model, build, and measure
Likely good repeatability
Don’t need to answer the detailed technical questions
Con:
Probably not the most accurate but should capture the main HF crosstalk effects
Are the technical assumptions acceptable?