1. Chapter 2.
High-speed properties of logic gates

2. 2.1 Historical development of very old digital tech.
Relays can switch large current signals.
For fast switching, the signal currents should be large.
Packaging and switching speed is limited by heat dissipation.
Fast switching → Heat(cooling) problem, Power loss.
Relay
With wire spring, separate assemblies for spring and contact armature are not needed.
Wire spring relay
Available models are 750Ω or 2400Ω coils with the standard 48V spec.

3. Relay

4. Trade-offs for high speed design
Standard packaging of logic devices saves money in manufacturing but reduces flexibility. The initial investment required for a new package type is staggering.
Standard packaging limits both the number of gates and the number of pins per package. Those factors force designers to partition large systems among many device packages. Signal connection between packages respond more slowly and consume more power than connections internal to one package.
The maximum allowable power dissipation per package is limited by a combination of package construction and the cooling.
Higher density packaging has the benefit of cutting assembly cost and product size. But maximum allowable power dissipation per package constrains the number of gates per package.
Speed and power in a given technology are somewhat interchangeable.

5. 2.2 Power consumption TTL (Transistor transistor logic)
출력이 high인 경우 Q1 conduct
출력이 low인 경우 Q2 conduct
High input: Forward active
Low input : Reverse active
Source
Sink

6. DTL (Diode transistor logic)
Low power Schottky TTL

7. Power dissipation
1. Quiescent dissipation : power consumed to hold a circuit in one logic state or the other.
2. Active power when driving a capacitive load.

8. Active power due to overlapping bias currents
TTL case
Totem pole stage
Q1, Q2가 함께 on 되는 상태에서 매우 큰 전류가 흐르고, 전력 소모가 많아진다.
For TTL circuits, the overlap effect is more pronounced. TTL circuits are not good candidates for use as linear, small signal processing elements(like oscillators) because they draw excess power in the linear state. ECL is more preferable.

9. CMOS case
CMOS인 경우 출력이 high 또는 low상태이면 전력 소모 0 이지만, switching이 일어나는 경우 Q1, Q2가 함께 on 되는 상태에서 전력 소모가 생긴다.

10. Power consumption of logic gates
Input power
Internal dissipation
Drive circuit dissipation
Output power
Each of the categories subdivide into active and quiescent dissipation.

11. 2.2.4 Input power
Quiescent input power is determined by multiplying the required input current by the power supply voltage.
Input power is relatively low. Those powers are significant only when many gates are connected in parallel. (Large fan out case)

12. 2.2.5 Internal dissipation
Internal power is used to bias and switch nodes internal to a logic device. Internal power includes both quiescent and active power dissipation.

13. 2.2.6 Drive circuit dissipation
Totem pole
Emitter follower
Open collector
Current source

14. Quiescent power dissipated in a totem-pole output
TTL case

15. CMOS case

16. Example 2.1

17. Active power dissipated in a totem-pole output
AC fan-out is related to the rising time or falling time.

18. Example 2.2
50 Ω impedance lines
74HCT640의 maximum propagation delay 가 9ns 일 때 20개의 fan-out 상태에서 33MHz (30ns)로 동작 가능여부?
Gate당 입력 단의 capacitance는 10pF. Line의 inch당 용량은 2pF임

19. Power dissipation in each driver
AC fan-out
53ns정도의 rising/falling time이 필요하므로 33MHz에서는 신호가 제대로 올라가고 내려올 시간적 여유가 없음. 53ns를 확보하려면 16MHz정도로 주파수를 낮출 필요 있음.
Power dissipation in each driver
IC package 1개의 Power dissipation을 고려하면 16MHz 동작도 어려움.

21. ECL
High : -0.9V
Low : -1.7V
ECL circuits need a pull-down resistor terminated to -5.2V or -2.0V

23. -5.2V로 pull down한 경우 소모 전력
-2V로 pull down한 경우 소모 전력

24. Pull down/up resistors
Transmission line에서 termination을 보는 경우임

25. Ringing ~
Signal source
Load
Mismatched load

26. Impedance matching - Digital
Source matching ~
Load matching ~

27. Open collector Wired-OR circuits
Since an open collector output "pulls" the output voltage from that of the pullup resistor to ground, many open-collector outputs can be wired together to create a wired-OR circuit.  This means that if any of these outputs are active, the combined output of all the gates will be ground.  This effects a logic-OR.  This can be useful when several outputs share a single line as would happen on a bus. 
Example wired-OR circuit using open-collector outputs of NAND gates.
Different Voltage Interfacing
Since the exact voltage of the pullup resistor is not critical, an open-collector output can be used to interface one logic voltage level with another. 
Example interface between 5V logic and a higher voltage.
You may also see the term open-drain output.  This is an open-collector output from a MOSFET which has a drain instead of a collector.  The basic idea is the same for open-collector and open-drain. 
The value of resistor used to pull up an open-collector is not critical.  Smaller values offer faster switching times at the price of higher current consumption.  Typical values range from a few thousand to a few hundred thousand Ohms. 
In circuit diagrams, logic gates are usually shown with an asterix (*) when the output is an open-collector or open-drain output. 

29. Current source output driver
CPU
clock
Data buffer D Q
Data bus
Data
Memory
RS-232
HDD
Chip select
Address decoder
Address
Address bus

30. Totem pole output driver인 경우 문제점
Signal contention

31. 486 mother board

32. 2.3 Speed
Theoretical digital logic design : focuses on the propagation delay
Practical problems depend on → minimum output switching time.
Fast switching times → problems due to return currents, crosstalk, ringing
Independent of propagation delay
Logic families with minimum switching times much faster than the propagation delay suffer an unnecessary penalty in system design
→ device packaging, board layout, connectors accommodate fast switching times.

33. 2.3.1 Effects of sudden change in voltage, dV/dt
Fast switching time에 의한 문제를 줄이기 위해 switching time에 제한을 둔 logic family들도 있다.
fast switching 에 의한 문제를 전압 및 전류로 나누어 생각할 수 있다.
2.3.1 Effects of sudden change in voltage, dV/dt
fknee 는 rising time에만 관련 있고, propagation delay, clock rate, switching frequency등과는 무관하다.
fknee 가 너무 높으면 signal propagation에서 문제를 일으킨다.
Mutual capacitance에 의한 crosstalk유발.

34. 2.3.1 Effects of sudden change in current, dI/dt
Mutual inductance에 의한 crosstalk유도.

35. 2.3.3 Voltage margins

36. Need for noise margin
DC power supply current, flowing through the DC resistance of the ground path, cause ground voltage differentials between logic devices.
Fast changing return signal currents, flowing through the inductance of a ground path, cause ground voltage differentials. (inductive crosstalk).
Signals on adjacent lines may couple through either mutual capacitance or (more likely) mutual inductance to a given line, generating crosstalk.
Ringing, or reflection, on long lines distorts the appearance of binary signals. Signal transitions may appear smaller (or larger) at the receiver than at the transmitter.
The threshold levels on some logic families are a function of temperature.
Noise margin percentage

37. 2.4 Packaging 2.4.1 Lead inductance – ground bounce Output voltage
= Vout+VGND

38. Ground bouncing

39. Measurement of ground bouncing

40. Chip mounting method

41. DIP
PLCC
BGA

42. 2.4.2 Lead capacitance
With fast rising time and higher input impedance level of victim, crosstalk become larger.

44. Ideal electronic system
전자 부품의 power line과 signal line이 분리되어 있음
Power line
Vcc + -
Signal line
GND
Power line 요구 사항 : 부품의 상태에 상관 없이 일정한 전압 출력을 내야 한다.
Signal line 요구 사항 : 신호 성분만 포함하며, 왜곡이 없으며 전파 방사가 적고, 내성이 강해야 한다.
두 line이 서로에 영향을 끼치지 않도록 배선되는 경우 이상적인 시스템 구현이 가능하다.

45. Physical wires/lines + - 실제 line들은 inductance와 저항을 갖고 있다.
Amp나 logic gate들은 power line과 signal line이 GND 를 공유한다.

46. Physical power lines on PCB
Vcc + -
Power
supply
Signal line
GND
Physical voltage source with line traces
Ideal voltage source
Power noise
또한 배선의 편의를 위해서 power line과 signal line이 같은 GND를 공유하게 되는 것이 문제다.

47. Properties of physical power lines
Vcc + -
Power
supply
Signal line
GND
Line의 임피던스 때문에 power line에 일정한 전류가 흐르는 동일한 copper 상이어도 전압이 다르다.
Logic gate 또는 amp가 동작 상태에 따라 전원 line에서 끌어들이는 전류가 다르기 때문에 voltage spike가 생긴다.
Signal line과 voltage reference를 공유하므로 동작 상태가 바뀌면 power line의 spike가 signal line에도 영향을 준다.

48. Building ideal power lines on PCB
Physical voltage source with line traces
PWR/GND plane capacitance
Power noise
L (Inductance)이 줄어들기는 하나 완전히 0이 되지는 않는다.
Inductance를 줄이기 위해 선 폭을 늘림

49. Power line noise due to line inductanceVA VA 5V +
VCC -
Vin 5V
Vin
Power line의 inductance 와 logic gate의 동작 상태에 따른 소모 전류의 변화 때문에 noise생김.

50. Ground bouncing noise
Ground bouncing noise

51. Decoupling capacitors
PWR line
inductance
Decoupling capacitor + -
(예제) 3.3V logic이고 rising time이 1ns, Δv = 0.3 V 일 때 + -

52. Transmission line approach
Power line의 inductance 와 capacitance를 transmission line으로 보는 관점.
Current wave +
VCC - ~

53. ADS simulation : no decoupling cap.

54. ADS simulation : with decoupling cap.

55. Line inductance에 대한 대책 + VCC -
Capacitor를 병렬로 달아 놓으면, 순간적인 전류의 변동은 capacitor가 담당하여 전압 spike가 생기지 않는다. VA +
VCC -
Vin
Vin VA
Vin

57. Self resonant frequency of SMT capacitors
Multiple parallel capacitors
Self resonant frequency of SMT capacitors

58. Line inductance에 의해 gate A의 동작에 따라 B의 전압이 바뀐다.
Effect of multiple components A B +
VCC - VB 5V VA +
VCC -
Vin
Vin 5V
Vin 58
Line inductance에 의해 gate A의 동작에 따라 B의 전압이 바뀐다.

59. Isolation of device power lines using ferrite bead
Transmission line에 흐르는 전류의 변동을 거의 없게 한다. +
VCC -
Transmission line에는 DC 전류만 흐르게 한다.
좀 더 적극적으로 filtering 하려면 ferrite bead를 연결한다. +
VCC - 59

60. Common ground return current path
인접 신호와 섞임
GND
GND/VCC
Return current 경로가 넓음.
Double sided board
GND/VCC 60
두 line이 인접한 경우 return current 중첩됨.
(Bad for high speed design)

61. Impedance reduction due to mutual inductance
Line trace와 GND 사이의 간격을 좁히면 k가 커져서 line 임피던스가 줄어든다.
☺ Line trace와 GND 사이의 mutual inductance가 클 수록 Zin은 작아진다.

62. Isolation of nearby return currents
두 line 사이의 mutual inductance 보다 각각의 line과 GND사이의 mutual inductance를 훨씬 크게 만들면 return current가 섞이는 것을 막을 수 있다. 62

63. Multi-layered PCB 배선이 복잡한 경우 multi-layer board를 만든다.
Multi-layer board에서 power plane과 GND plane은 parallel plate waveguide 구조를 형성하므로 propagating mode가 생기지 않도록 조치를 취한다. 63

64. Multi-layered circuit board example64

65. Mode suppression by decoupling caps or vias
VCC
GND
High frequency 에서 C가 있는 지점에서 electric field null이 생김.
안생김
VCC
Cap
GND
GND
Via
GND 65
Low frequency 에서 via가 있는 지점에서 electric field null이 생김.

66. Mixed signal PCB – split ground
GND
GND
Analog
(small signal)
Digital
(Large signal) + -
Digital 회로의 large signal switching에 의한 ground noise가 amplitude가 작은 analog회로에 영향을 끼치는 것을 막기 위해 split ground를 썼다.
이 경우 주의해야 할 점은 analog/digital interface이다. Signal line과 함께 전압의 기준선인 GND선도 함께 연결되어야 한다. 66

67. Analog/Digital interface
GND
Analog
(small signal)
Digital
(Large signal) + -
잘못된 방법
GND 선을 signal line에 인접하게 배치하지 않은 경우 current loop의 면적이 커져 radiation되는 전파가 많아진다. 67