WP6 status report A. Di Mauro (CERN) ITS plenary meeting 20.01.2014.

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Presentation transcript:

WP6 status report A. Di Mauro (CERN) ITS plenary meeting

Outline Update on development of FPC in Al Summary of proposal of an automated HIC assembly system from VEA Planning of 2014 WP6 objectives 20/01/2014WP6 status report - A. Di Mauro2

Status of Al-FPC R&D 7 prototypes have been etched using DEPHIS Al-coated kapton (the first was shown in December); however last step (Ni/Au coating of contacts) failed due to issues with quality of Al layer (too porous). New foils are being prepared by DEPHIS by improving the Al processing. Two kapton foils coated (with 25  m Al) by FHR were delivered last week and will be processed in the next two weeks. 3 20/01/2014WP6 status report - A. Di Mauro

Al-FPC deformation -Nominal distance between first and last contact: mm -Metrology checks along 5 trace lines 20/01/2014WP6 status report - A. Di Mauro4 C1 C2C3 C4 C5 C6C7 C9 C10C11 C13 C14C15 C17 C18C19 C20

Al-FPC deformation -Al coating and subsequent steps produce shrinking (observed up to ~400 mm): -Cu FPC (12/09/2013): , , , , Al FPC (DEPHIS prototype, after etching, 16/12/2013): , , , , Al FPC (FHR 15μm Al, before etching, 07/01/2014): , , , , After finalization of the production procedure, will study various solutions depending on reproducibility of effect and final deviation from nominal value: -Pad diameter larger than FPC holes (e.g., 250  m pad can compensate 100  m over 9 chip flex) -Modify holes position when drilling in order to achieve final nominal values -Compensate by suitable adjustment of chips gap (variation of chips position HIC by HIC!) 20/01/2014WP6 status report - A. Di Mauro5

Automated HIC assembly system from VEA The proposal has been reviewed and the system is conform to our requirements and suitable to the purpose. The main constraints are precision (final chip position tolerance ~ 5-10  m) and time In order to achieve the required accuracy and repeatability Linear Positioning Stages (X,Y,Z) have been preferred to robotic arms (faster but less precise) The structures are simple and also the mathematical model to compensate errors due to thermal expansion is quite simple This machine allows the assembly of both modules for the inner layer (1 x 9 chips) and for the outer layer (2 x 7 chips) by simple replacement of the "assembly frame", the "FPC stack" and the “soldering balls grid“. 20/01/2014WP6 status report - A. Di Mauro6

20/01/2014WP6 status report - A. Di Mauro7 TOP VIEW SIDE VIEW X or Y Linear Positioning Stage -200 mm/s mm unidirectional repeatability -0.2 mm bidirectional repeatability 7 Z LPS with 0,1 μm unidirectional repeatability Automated HIC assembly system from VEA

20/01/2014WP6 status report - A. Di Mauro88 Automated HIC assembly system from VEA Ultra high-precision rotation stage - ± 1.7  rad ( o ) repeatability The assembly frame is positioned on a high precision rotation stage and it has vacuum suction to hold components.

20/01/2014WP6 status report - A. Di Mauro99 Automated HIC assembly system from VEA Cycle time estimation PhaseNormal time (s) Pessimistic time (s) Chip placement FPC placement Soldering balls grid placement Soldering balls placement (group of 22) Laser soldering (time per contact)510 Worst case scenarios: -9 chips → 9x x(4x10.5) + 9x(88x10) = 8388” = ~ 2 h 20’ -2x7 chips → 14x x(4x10.5) + 14x(88x10) = 13039” = ~ 3 h 38’ Assuming 48+10% HICs for IB and % HICs for OB and 16 h/ working day: 8 days for IB days for OB

2014 WP6 objectives 20/01/2014WP6 status report - A. Di Mauro10 TaskWP6 specific topic/ issue ResourceMilestone (TBC) Finalization of IB geometry (with inputs from WP1 and WP2) and layout (with WP9 and WP10) FPC extension for E-o-C row A. Junique A. Di Mauro C. Gargiulo Mar 14 Finalization of design and characterization of FPC -Al coating/etching -Trace params and routing -Power and signal connection A. Junique M. Keil Jun 14 Development of HIC assembly and test procedure and set-up (with WP4 and WP7-8) Automated system J. Van Beelen P. Ijzermans P. Riedler A. Di Mauro Jul 14 Development of prototype of IB staves based on “pad chips”, dimensional survey and characterization (mechanical and thermal) (joint project with WP9) Sep 14 Development and characterization of stave based on FS-ALPIDE. Nov 14 Document on dimensional and position survey procedure (joint with WP7, WP8 and WP9) Nov 14

WP6 meetings Weekly on Thursdays, 15:30 (Geneva Time) At CERN: 4-S-030 Next Meeting: Jan 30 20/01/2014WP6 status report - A. Di Mauro11