1. Phase 2 Tracker R&D Background: Initial work was in the context of the long barrel on local tracklet- based designs. designs of support structures and PS modules based on 3D integrated circuits. Including thermal testing and simulation. Design of off-detector FPGA track formation logic which accommodates 6.4 microsecond L1 accept simulation of tracklet and track formation Verilog design of the readout chip. VICTR 3D chip prototyping and testing Interposer development and testing Active edge sensor R&D Decision to drop long barrel and restrict tracker geometry means that we have had to rethink our program. R. Lipton1

2. Outline for Phase 2 Tracker R&D Proposal PS Chip design and Test Collaborate on the design – Simulate chip function using Verilog with GEANT simulation input (CU, FNAL) – Provide physics input (CU) – Develop subcircuits as agreed, prototype micropipeline designs in the pixel test chip (FNAL) Chip testing – Test prototype chips (BU, CU) – Test micropipelines (BU) – Complete VICTR tests (CU) TSV Development Collaborate with CERN on an alternate vendor (Allvia) for a via-last design – Test CERN modules (BU) – Develop double sided probing?(FNAL) Develop an interposer using TSVs for PS module (FNAL, UCD) DC-DC Converter Development Demonstrate and test converted with pcb imbedded coils (FNAL, Yale) Explore LDMOS components for suitability (FNAL, Yale, Brown?) R. Lipton2 Module Development Layout possible flex solution (FNAL, UCD) Layout possible silicon solution (FNAL, UCD) Demonstrate large area bump bonding (UCD) Build mechanical prototypes (FNAL, UCD) Off-Detector Track Finding Develop test stands (FNAL, CU) Continue tracklet-based FPGA solution demonstration (CU) Develop track fitter module (CU) Study alternatives to pure AM technique (CU, FNAL, BU) Active Edge Complete fabrication and test of VTT/CU modules (UC, FNAL, BU) Beam tests (FNAL, CU, BU) Study edge properties of etched test structures (CU, FNAL) Design wafer-scale demonstration (FNAL, CU, BU) Development of radiation length measurement facility?

3. Last year R. Lipton3 Labor M&S FY13 request Original FY13 allocation Current Allocation FY13 request Original FY13 allocation Current Allocation Brown25,221.0025221 40004,000.004000.000 Cornell51,200.202841951,200.20187508,750.0018750.000 UC Davis42,505.0036184?2690012,900.0012900.000 Fermilab84,210.0021250 11500012,500.0095000.000 UCSB?36184?35003,500.003500.000

4. Feasibility - Time Scales PS module design + interconnect – 6 months – mechanical + thermal study – PCB prototypes – 9 months – Bonded stacks – 1.5 year Track Finding – 1 year – test stands at Cornell – 9 months study of tracklets in barrel disk Readout chip – Verilog design – 6 months – Prototypes – 2 years Mechanics Active Edge – 9 months study dRIE on test structures – 1.5 years – full demonstration R. Lipton4

5. Technical Challenge – PS Module design Spacing between layers will vary with radius and between barrel and disk modules We would like to continue to work on a design based on either TSVs or a PC board interposer that solves many of these problems Collaborating with CERN on development of a commercial TSV vendor in the US – Received wafers this week – Chip Testing at Cornell R. Lipton5 Current PS module design needs considerable development to be thermally, mechanically and functionally acceptable It is essentially a pixel detector, so one sensor has to be bump bonded to readout chips – Cooling should have minimum thermal impedance – Interconnections are needed between columns of chips to insure full coverage – Z information must cross between chips or incur dead regions – Information from the bottom sensor has to be transmitted to the top (or vice-versa)

6. Technical Challenge- Interconnect Explore PCB-based interposer design using flex circuit – Discussions with companies on technologies and prototypes – Understand requirements (via size, line width, layers) for successful layout – Understand CTE issues – Understand bonding issues R. Lipton6

7. Geography Had an initial look at a design with fan-in – Very difficult with standard PCB design rules – OK if we use silicon interposer with smaller features Look at simplest (cheapest) design – Keep same pitch on PCB as sensor – Move pads outboard to provide space for digital in center – Gang inner 2 pixels to simplify routing (can be changed with more complex routing) – Simple connection between pixel and PCB R. Lipton7 Top side Bottom sensor

8. Proposed Structure R. Lipton8 Top sensor bottom sensor Flex interconnect To PCB PCB/flex ROICs

9. R. Lipton9 Top sensor Flex interconnect To PCB PCB/flex ROICs bottom sensor Readout interconnect

10. R. Lipton10 Top sensor PCB/flex ROICs bottom sensor ROICs Digital bus area Digital I/O

11. R. Lipton11 Bottom sensor interconnects Top sensor interconnects

12. R. Lipton12 Bottom sensor interconnects Top sensor interconnects Flex foldover

13. R. Lipton13

14. Rectangular arrays R. Lipton14

15. 1/2 mil lines 2 mil holes in interposer R. Lipton15

16. Module R. Lipton16 Dummy ROICFlex foldover Carbon foam Dummy sensors Kapton spacers Carbon foam/flex based design