Distributed Computation: Circuit Simulation CK Cheng UC San Diego

Trends of Scaling (Moore’s Law) Expansion of applications: ai, bioinf, graphics, vision Explosion of communication: internet Distributed system: exascale computation Power constrained designs: low power Interconnect dominance: VLSI Nano-devices with variations: fault tolerant design, design for manufacturability 2 Technology System Application

Research Outline Parallel SPICE – Cluster Machines – Netlist Partitioning – Whole Chip Analysis – SPICE Accuracy Power Ground Analysis – Worst Power Load Exploration – 3D Power Distribution – Voltage Drop and Electronic Migration Analysis – RLC Optimization 3

Circuit Simulation: Motivation Technology Scaling Challenges for Circuit Simulation  Complexity  Signal Integrity: crosstalk, voltage drop, coupling noise etc.  High clock frequency: Inductance Effect  Smaller transistors: Higher nonlinearity

Simulation: Goal Analyze whole chip with 100x memory capacity, 100x speed up, 100x efficiency for designers Set standard of input/output for parallel processing Allow cluster machines or cloud computing for the acceleration Demonstrate the results via power ground analysis and tera Hertz circuitry 5

Parallel Device Loading (continued) Original Circuit Nonlinear Sub-circuit Interface Linear-Nonlinear Iteration linear Sub-circuit … … Equivalent Ckt PU: Processing Unit linear Sub-circuit Equivalent Ckt linear Sub-circuit Equivalent Ckt PU K+j1 Parallel AMG PU K Parallel AMG PU K+jm Parallel AMG PU 1 Direct Solver (KLU) Nonlinear Sub-circuit Equivalent Ckt PU 2 Direct Solver (KLU) Nonlinear Sub-circuit Equivalent Ckt PU k-1 Direct Solver (KLU) Device Loading

Action Items Input/Output Parsing and Screening – Parallel Input Parallel input format Parallel parsing – Netlist Transformation – Parallel Output Output parsing Graphic display Device Evaluation – Transistor Model Matrix Solver Sensitivity Calculation Adaptive Time Step Control Parallelization Overall Framework – Implement in C/C++ – Which math library? – Sparse matrix library? – Parallel Implementation Applications – Power Ground Network Analysis – Tera Hertz Circuit Simulation 7

Power Grid Analysis Package: – Voltage regulator – distributed RLC model Silicon Chips: – Bumps – Metal wires

Power Network Analysis: Motivation 9 Yeargte L nm freq GHz Vdd Volt PWPW I=P/V Amp Z=V/I Ohm ITRS Roadmap: MPU

Responses in Frequency Domain T1 T2 γ=0γ=0 γ= 0.05 γ=1

Time Domain Responses: Rogue Waves

Conclusion Spice Simulation for Whole System – Memory Capacity – CPU Time – User Interface Power Distribution Analysis – Huge Netlist – Complex Electrical Behavior – Stringent Constraints 12