1. Chapter 2 Interconnect Analysis Delay Modeling
Prof. Lei He
Electrical Engineering Department
University of California, Los Angeles
URL: eda.ee.ucla.edu

2. Outline Delay models RC tree Elmore delay Gate delay Homework 2
ECE902 VLSI Interconnect
Outline
Delay models
RC tree Elmore delay
Gate delay
Homework 2
Prepared by Lei He

3. Input-to-Output Propagation Delay
The circuit delay in VLSI circuits consists of two components:
The 50% propagation delay of the driving gates (known as the gate delay)
The delay of electrical signals through the wires (known as the interconnect delay)

4. Lumped vs Distributed Interconnect Model
ECE902 VLSI Interconnect
Lumped vs Distributed Interconnect Model
Lumped
Distributed R C r c
How to analyze the delay for each model?
Prepared by Lei He

5. Lumped RC Model R
v(t)
u(t) C
Impulse response and step response of a lumped RC circuit

6. Analysis of Lumped RC Model
ECE902 VLSI Interconnect R C
S-domain ckt equation (current equation)
Frequency domain response for step-input
Frequency domain response for impulse
match initial state: v0
v0(1-eRC/T)
Time domain response
for step-input:
Time domain response
for impulse:
Prepared by Lei He

7. 50% Delay for lumped RC model
V(t) 1v 1
0.5
50% delay
How about more complex circuits?

8. Distributed RC-Tree The network has a single input node
ECE902 VLSI Interconnect
Distributed RC-Tree R1 C1 s R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i
The network has a single input node
All capacitors between node and ground
The network does not contain any resistive loop
Prepared by Lei He

9. ECE902 VLSI Interconnect
RC-tree Property R1 C1 s R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i
Unique resistive path between the source node s and any other node i of the network  path resistance Rii
Example: R44=R1+R3+R4
Prepared by Lei He

10. RC-tree Property Extended to shared path resistance Rik:
ECE902 VLSI Interconnect
RC-tree Property R1 C1 s R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i
Extended to shared path resistance Rik:
Example: Ri4=R1+R3
Ri2=R1
Prepared by Lei He

11. The Elmore delay at node i is:
ECE902 VLSI Interconnect
Elmore Delay
Assuming:
Each node is initially discharged to ground
A step input is applied at time t=0 at node s
The Elmore delay at node i is:
Theorem: The Elmore delay is equivalent to the first-order time constant of the network
Proven acceptable approximation of the real delay
Powerful mechanism for a quick estimate
Prepared by Lei He

12. Example Elmore delay at node i is 2 R2 R1 C2 4 1 s R4 R3 C4 C1 3 Ri C3
ECE902 VLSI Interconnect
Example R1 C1 s R2 C2 R4 C4 C3 R3 Ci Ri 1 2 3 4 i
Elmore delay at node i is
Prepared by Lei He

13. Interpretation of Elmore Delay
ECE902 VLSI Interconnect
Interpretation of Elmore Delay
median
of h(t)
(T50%)
h(t) = impulse response
H(t) = step response
Definition
h(t) = impulse response
TD = mean of h(t) =
Interpretation
H(t) = output response (step process)
h(t) = rate of change of H(t)
T50%= median of h(t)
Elmore delay approximates the median of h(t) by the mean of h(t)
Prepared by Lei He

14. Elmore Delay Approximation

15. RC-chain (or ladder) Special case:
ECE902 VLSI Interconnect
RC-chain (or ladder)
Special case:
Shared-path resistance path resistance R1 C1 R2 C2 RN CN
Vin VN
Prepared by Lei He

16. RC-Chain Delay Delay of wire is quadratic function of its length
ECE902 VLSI Interconnect
RC-Chain Delay R C R C R C
Vin VN
R=r · L/N
C=c·L/N
Delay of wire is quadratic function of its length
Delay of distributed rc-line is half of lumped RC
Prepared by Lei He

17. Outline Delay models RC tree Elmore delay Gate delay Noise models
ECE902 VLSI Interconnect
Outline
Delay models
RC tree Elmore delay
Gate delay
Noise models
Prepared by Lei He

18. Gate Delay and Output Transition Time
The gate delay and the output transition time are functions of both input slew and the output load

19. General Model of a Gate

20. Definitions Output Transition Time Gate Delay Vin Vout Time 90% 10%W p n C M
out
Cdiff
Cload
Vin
Vout
Cout

21. Output Response for Different Loads

22. Output Transition Time
Input Transition Time (s)
Output Transition time (s)
10-10
CLoad (F)
10-14
Output transition time as a function of input transition time and output load

23. ASIC Cell Delay Model
Three approaches for gate propagation delay computation are based on:
Delay look-up tables
K-factor approximation
Effective capacitance
Delay look-up table is currently in wide use especially in the ASIC design flow
Effective capacitance promises to be more accurate when the load is not purely capacitive

24. Table Look-Up Method
115pS
What is the delay when Cload is 505f F and Tin is 90pS?

25. K-factor Approximation
Input Transition Time (s)
Output Transition time (s)
10-10
CLoad (F)
10-14
We can fit the output transition time v.s. input transition time and output load as a polynomial function, e.g.
A similar equation gives the gate delay

26. One Dimensional Table
Linear model

27. Two Dimensional Table D1 D4 D3 D2
Quadratic model

28. Second-order RC-p Model
Using Taylor Expansion around s = 0

29. Second-order RC-p Model (Cont’d)
This equation requires creation of a four-dimensional table to achieve high accuracy
This is however costly in terms of memory space and computational requirements

30. Effective Capacitance Approach
The “Effective Capacitance” approach attempts to find a single capacitance value that can be replaced instead of the RC-p load such that both circuits behave similarly during transition

31. Output Response for Effective Capacitance

32. Effective Capacitance (Cont’d)

33. Effective Capacitance (Cont’d)
0<k<1
Because of the shielding effect of the interconnect resistance , the driver will only “see” a portion of the far-end capacitance C2 Rp
k = 1
Rp ∞
k = 0

34. Effective Capacitance for Different Resistive Shielding

35. Macy’s Approach
Assumption: If two circuits have the same loads and output transition times, then their effective capacitances are the same
=> the effective capacitance is only a function of the output transition time and the load

36. Macy’s Iterative Solution
Compute a from C1 and C2
Choose an initial value for Ceff
Compute Tout for the given Ceff and Tin
Compute b
Compute g from a and b
Find new Ceff
Go to step 3 until Ceff converges

37. Summary Delay model Elmore delay
Gate delay: look-up table, k-factor approximation, effective capacitance 37

38. References
R. Macys and S. McCormick, “A New Algorithm for Computing the “Effective Capacitance” in Deep Sub-micron Circuits”, Custom Integrated Circuits Conference 1998, pp
J. Cong, Z. Pan and P. V. Srinivas, "Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization", Asia and South Pacific Design Automation Conference 2001, pp
L. H. Chen, M. M.-Sadowska, “Aggressor Alignment for Worst-case Coupling Noise”, International Symposium on Physical Design 2000, pp 38

39. Homework
[1] Given the circuit as shown below and a unit step voltage source at the input node s, use SPICE to simulate the circuit and obtain the accurate 50% delay at node n. Also analytically calculate the delay using Elmore method and S2P method. How do they compare with the result obtained by SPICE? R1 C1 s R2 C2 R4 C4 C3 R3 C5 R5 n
R1 = 1mΩ
R2 = 2mΩ
R3 = 2mΩ
R4 = 1mΩ
R5 = 4mΩ
C1 = 1nF
C2 = 1nF
C3 = 4nF
C4 = 4nF
C5 = 2nF 1v

40. Homework
[2] Give the circuit as shown below and a unit step voltage source at node s, can we still use the “shared-path” formula to calculate the Elmore delay? Explain why or why not. Use DC analysis method via MATLAB or SPICE to get the 0th -3rd moments of C3 and C5. R1 C1 s R2 C2 R4 C4 C3 R3 C5 C6 n
R1 = 1mΩ
R2 = 2mΩ
R3 = 2mΩ
R4 = 1mΩ
C1 = 1nF
C2 = 1nF
C3 = 4nF
C4 = 4nF
C5 = 2nF
C6 = 1nF 1v 40

41. 3. Use the Elmore delay formula to calculate the Elmore delay.
Steps for Problem 1
1. Write the SPICE netlist of the circuit and probe the voltage response at node n.
2. Record the time when the voltage at node n reaches 0.5V. That time is the 50% delay.
3. Use the Elmore delay formula to calculate the Elmore delay.
(find the shared path between each node and node n).
4. Write down the transfer function and driving point admittance of the circuit with input s and output n.
5. Expand the transfer function to get the moments m1* and m2*. Expand the driving point admittance to get m1, m2, m3, and m4. 41

42. 6. Follow the S2P algorithm to get k1, k2, p1 and p2.
Steps for Problem 1
6. Follow the S2P algorithm to get k1, k2, p1 and p2.
7. Use the frequency domain expression (h(s)) to derive the time domain expression (h(t)).
8. Plot the obtained time domain waveform to get the 50% delay for the S2P model.
9. Compare the results. 42

43. 3. Get the voltage across the capacitance as the moment.
Steps for Problem 2
1. Follow the DC analysis method to reconstruct the circuit (e.g. replace C with zero current source for 0th moment calculation, etc).
2. Stamp the G and C matrices for MATLAB analysis or write the corresponding netlist for SPICE analysis.
3. Get the voltage across the capacitance as the moment.
4. The above should be done repeatedly until all the desired moments are acquired. 43

44. Homework 2
[3] Modify the PRIMA code with single frequency expansion to multiple points expansion. You should use a vector fspan to pass the frequency expansion points. Compare the waveforms of the reduced model between the following two cases: 1. Single point expansion at s=1e4. 2. Four-point expansion at s=1e3, 1e5, 1e7, 1e9. 44

45. Format of the input matrices for test
e-15
e-15
e-15
e-13
e-13
e-15 e
e-13
e-13
….. 45

54. G,C,B,U,L matrices have been generated. Prima begins: Elapsed time is seconds. Prima done! Calculate original time domain response: Elapsed time is seconds. Original time domain response done! Calculate reduced time domain response: Elapsed time is seconds. Reduced time domain response done! Calculate original frequency response: Elapsed time is seconds. Original frequency response done! Calculate reduced frequency response: Elapsed time is seconds. Reduced frequency response done! Calculate original impulse response: Elapsed time is seconds. Original impulse response done! Calculate reduced impulse response: Elapsed time is seconds. Reduced impulse response done!