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Transistors on lead microprocessors double every 2 years
Moore’s Law in Microprocessors Transistors on lead microprocessors double every 2 years 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 0.001 0.01 0.1 1 10 100 1000 1970 1980 1990 2000 2010 Year Transistors (MT) 2X growth in 1.96 years!
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Evolution in DRAM Chip Capacity
4X growth every 3 years! 0.07 m 0.1 m 0.13 m m m m m m m
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Die size grows by 14% to satisfy Moore’s Law
Die Size Growth Die size grows by 14% to satisfy Moore’s Law 4004 8008 8080 8085 8086 286 386 486 Pentium ® proc P6 1 10 100 1970 1980 1990 2000 2010 Year Die size (mm) ~7% growth per year ~2X growth in 10 years
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Lead microprocessors frequency doubles every 2 years
Clock Frequency Lead microprocessors frequency doubles every 2 years 10000 2X every 2 years 1000 P6 100 Pentium ® proc 486 Frequency (Mhz) 10 386 8085 286 8086 8080 1 8008 4004 0.1 1970 1980 1990 2000 2010 Year Courtesy, Intel
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Power Dissipation Lead Microprocessors power continues to increase
100 P6 Pentium ® proc 10 486 286 Power (Watts) 8086 386 8085 1 8080 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year Power delivery and dissipation will be prohibitive
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Power density too high to keep junctions at low temp
4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 1 10 100 1000 10000 1970 1980 1990 2000 2010 Year Power Density (W/cm2) Rocket Nozzle Nuclear Reactor Hot Plate Power density too high to keep junctions at low temp
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Complexity outpaces design productivity
Design Productivity Trends 10,000 1,000 100 10 1 0.1 0.01 0.001 100,000 (M) Logic Tr./Chip 10,000 Tr./Staff Month. 1,000 58%/Yr. compounded Complexity 100 Complexity growth rate (K) Trans./Staff - Mo. Productivity Logic Transistor per Chip 10 x x 1 x x 21%/Yr. compound x x x Productivity growth rate x 0.1 0.01 2003 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2005 2007 2009 Complexity outpaces design productivity Courtesy, ITRS Roadmap
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SIA Roadmap Year 1999 2002 2005 2008 2011 2014 Feature size (nm) 180
130 100 70 50 35 Mtrans/cm2 7 14-26 47 115 284 701 Chip size (mm2) 170 235 269 308 354 Signal pins/chip 768 1024 1280 1408 1472 Clock rate (MHz) 600 800 1100 1400 1800 2200 Wiring levels 6-7 7-8 8-9 9 9-10 10 Power supply (V) 1.8 1.5 1.2 0.9 0.6 High-perf power (W) 90 160 174 183 Battery power (W) 1.4 2.0 2.4 2.2
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Design Abstraction Levels
SYSTEM MODULE + GATE CIRCUIT Vout Vin DEVICE n+ S D G
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Major Design Challenges
Microscopic issues ultra-high speeds power dissipation and supply rail drop growing importance of interconnect noise, crosstalk reliability, manufacturability clock distribution Macroscopic issues time-to-market design complexity (millions of gates) high levels of abstractions reuse and IP, portability systems on a chip (SoC) tool interoperability Year Tech. Complexity Frequency 3 Yr. Design Staff Size Staff Costs 1997 0.35 13 M Tr. 400 MHz 210 $90 M 1998 0.25 20 M Tr. 500 MHz 270 $120 M 1999 0.18 32 M Tr. 600 MHz 360 $160 M 2002 0.13 130 M Tr. 800 MHz 800 $360 M
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