EE141 © Digital Integrated Circuits 2nd Devices 1 Lecture 6. CMOS Device (cont) ECE 407/507.

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Presentation transcript:

EE141 © Digital Integrated Circuits 2nd Devices 1 Lecture 6. CMOS Device (cont) ECE 407/507

EE141 © Digital Integrated Circuits 2nd Devices 2 Notice  Reading Assignment : chapter 1, chapter 3 (finish reading)  Both hw1 and lab1 are on the website  hw1 due in one week (next Thurs.)  Lab1 due in two week (the Thurs. after next )

EE141 © Digital Integrated Circuits 2nd Devices 3

EE141 © Digital Integrated Circuits 2nd Devices 4

EE141 © Digital Integrated Circuits 2nd Devices 5

EE141 © Digital Integrated Circuits 2nd Devices 6 The Transistor as a Switch

EE141 © Digital Integrated Circuits 2nd Devices 7 The Transistor as a Switch

EE141 © Digital Integrated Circuits 2nd Devices 8 The Transistor as a Switch

EE141 © Digital Integrated Circuits 2nd Devices 9

EE141 © Digital Integrated Circuits 2nd Devices 10

EE141 © Digital Integrated Circuits 2nd Devices 11 C GCB_1 C GCS C GCD

EE141 © Digital Integrated Circuits 2nd Devices 12

EE141 © Digital Integrated Circuits 2nd Devices 13

EE141 © Digital Integrated Circuits 2nd Devices 14

EE141 © Digital Integrated Circuits 2nd Devices 15

EE141 © Digital Integrated Circuits 2nd Devices 16

EE141 © Digital Integrated Circuits 2nd Devices 17

EE141 © Digital Integrated Circuits 2nd Devices 18 The Sub-Micron MOS Transistor  Threshold Variations  Subthreshold Conduction  Parasitic Resistances

EE141 © Digital Integrated Circuits 2nd Devices 19 Threshold Variations V T L Long-channel threshold LowV DS threshold Threshold as a function of the length (for lowV DS ) Drain-induced barrier lowering (for lowL) V DS V T

EE141 © Digital Integrated Circuits 2nd Devices 20 Sub-Threshold Conduction V GS (V) I D (A) VTVT Linear Exponential Quadratic Typical values for S: mV/decade The Slope Factor S is  V GS for I D 2 / I D 1 =10

EE141 © Digital Integrated Circuits 2nd Devices 21 Sub-Threshold I D vs V GS V DS from 0 to 0.5V

EE141 © Digital Integrated Circuits 2nd Devices 22 Sub-Threshold I D vs V DS V GS from 0 to 0.3V

EE141 © Digital Integrated Circuits 2nd Devices 23 Summary of MOSFET Operating Regions  Strong Inversion V GS > V T  Linear (Resistive) V DS < V DSAT  Saturated (Constant Current) V DS  V DSAT  Weak Inversion (Sub-Threshold) V GS  V T  Exponential in V GS with linear V DS dependence

EE141 © Digital Integrated Circuits 2nd Devices 24 Parasitic Resistances

EE141 © Digital Integrated Circuits 2nd Devices 25 Future Perspectives 25 nm FINFET MOS transistor

EE141 © Digital Integrated Circuits 2nd Devices 26 New Tech: Silicon On Insulator (SOI)  Silicon wafers are highly perfect : critically important for achieving high device yield.  But a more radical change may be needed in the material structure, processing method, or device design in order to enhance the circuit performance.

EE141 © Digital Integrated Circuits 2nd Devices 27 Why use SOI  Extend the life of traditional silicon technology  Boost speed  Reduce power consumption  Solve some scaling difficulties

EE141 © Digital Integrated Circuits 2nd Devices 28 Transistor crosssection

EE141 © Digital Integrated Circuits 2nd Devices 29

EE141 © Digital Integrated Circuits 2nd Devices 30 SOI material structure SOI material structure

EE141 © Digital Integrated Circuits 2nd Devices 31

EE141 © Digital Integrated Circuits 2nd Devices 32

EE141 © Digital Integrated Circuits 2nd Devices 33

EE141 © Digital Integrated Circuits 2nd Devices 34

EE141 © Digital Integrated Circuits 2nd Devices 35 Benefits of SOI -performance

EE141 © Digital Integrated Circuits 2nd Devices 36 Benefits of SOI -- power

EE141 © Digital Integrated Circuits 2nd Devices 37 Benefits of SOI – timing

EE141 © Digital Integrated Circuits 2nd Devices 38 SiGe: Silicon Germanium  Used to be inefficient in chip production  Extremely high frequencies: 60Ghz  Very little power usage  70% faster, 35% less power

EE141 © Digital Integrated Circuits 2nd Devices 39 Why SiGe The layer of latticed silicon and germanium added to the chips silicon layer increases the distance between silicon atoms Less force between atoms, easy for electrons to pass by with less resistance IBM suggests combining SiGe and SOI

EE141 © Digital Integrated Circuits 2nd Devices 40 Thermal problem with SiGe Thermal problem with SiGe The diagram above shows the effect of localized self-heating in the emitters (30C for 40mv)