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Device Physics – Transistor Integrated Circuit
Lecture 7.1 Device Physics – Transistor Integrated Circuit
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Transistor Bipolar Transistor Field Effect Transistor (FET) Uses
Discrete device On Chip Field Effect Transistor (FET) Uses Amplify a signal Operational Amplifier Switch On/Off Process and store binary data
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Switch
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Bipolar Transistor Combination of two back-to-back p-n junctions P-N-P
N-P-N
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Bipolar Transistor
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Circuit Configurations
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Single PN Junction -Constant Gate Voltage
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Amplify Input Voltage Signal
Gain
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Amplifier Gain Common-base configuration current gain Voltage Gain
=1-(Wb/Lp)2/2 ~ 1 (slightly less than 1.0) Wb = width of base minus depletion regions Lp = diffusion length of holes in the base. Voltage Gain ce= /(1- ) (values from 400 to 600)
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FET- (Field Effect Transistor)
MOSFET Metal oxide semiconductor field effect transistor IGFET Insulated-gate FET NMOS or PMOS MISFET Metal-insulator-semiconductor FET MOST Metal-oxide semiconductor transistor JFET Junction FET
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MOSFET in Memory Chip Source Gate Drain
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Field Effect Transistor (FET)
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Voltage Controlled Resistor
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Inversion Zone - Poisson’s Eq.
2U = -/( o ) Metal on N Zone P Zone n= - e Nd -p=+ e Na Boundary Conditions U=Uo at x=0 U=0 V at x=
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Inversion Layer
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Electron Tunneling Electron Transmission, T, through thickness, δ.
U=Potential Energy of Barrier E=Total Energy of Electron
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Integrated Circuits CPU or Memory First Layer Multi-layer Transistors
Capacitors Diode Resistors Multi-layer Wiring Interconnects Bonding Pads Dielectric Heterostructures
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Transistor Switching Speed
PNP vs NPN N channel is Faster - NPN Mobility of n (electron is faster than hole)
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Much Lower Switching Power
Complementary MOS N channel connected to P channel 106 less power for switching 1 pnp acts as amplifier 2nd npn does the switching
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VT IS LESS for Complementary Transistor
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Integrated Circuit Good for the next 20 years!
By 2012 1 Billon Transistors/die 10 Ghz! Limitations by 2017 (gate Thickness) (Gordon E.) Moore’s Law, 1965 Doubling of transistor density every year! Doubling of computer speed in 18 months Doubling of computer size in 18 months Substantial decrease in price with time Price of transistor is 10-6 of original price
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Size of Transistor $1B/acre 5 layers of Metalization
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Scaling Parameter = S >1
Linear Dimension L1L1/S Reduce all linear dimenstions by 1/S Reduce voltage by 1/S Increase doping Concentrations by S Decrease time for electron to cross gate t = L1/Vdrift t/S, Vdrift= eE/me , =relaxation time Power Dissipated per transistor P = I V (I/S)(V/S) P/S2
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Computer Speed Switching Time RC delay time of Interconnects
Time to take an electron across a gate t = L/Vdrift Vdrift= eE/me , =relaxation time t t/S RC delay time of Interconnects Resistance R= L/A R= L*S/A/S2 RS3 Capacitance C=oA/d C =o(A/S2)/(d/S) C/S RC RCS2
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Copper Wiring/Low K dielectric
Pentium IV S < 0.18 μm >2.0 Ghz
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What a Memory Chip Looks Like
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DRAM memory Array Memory Chip First Layer Multi-layer Transistors
Wiring Interconnects Bonding Pads Dielectric Capacitors
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Reading and Writing Think of a memory chip as a grid or array of capacitors located at specific rows and columns. If we choose to read the memory cell located at row 3, column 5, we will retrieve information from a specific capacitor. Every time we go to row 3, column 5, we will access or address the same capacitor and obtain the same result (1) until the capacitive charge is changed by a write process.
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DRAM Memory Cell 1 Bit Column Line Capacitor Gate or Row Line
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READ
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WRITE
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