Sub-Nyquist Sampling Algorithm Implementation on Flex Rio High Speed Digital Systems Lab Sub-Nyquist Sampling Algorithm Implementation on Flex Rio Part A Final Presentation By : Genady Paikin, Ariel Tsror Supervisors : Inna Rivkin, Rolf Hilgendorf Powerpoint Templates

Agenda Introduction Learning Process Environment LabView LabView Problems JTag/ChipScope

Agenda Hardware System Implemented Blocks Xilinx Synthesis Part B Blocks System Verification Methods Full System Integration

Introduction The project is part of the Sub-Nyquist sampling and reconstruction card. Our goal is to implement DSP unit on FlexRio FPGA cards under NI LabView environment. Includes integration to the full system. Ariel Introduction

High Level Architecture Xampling ariel Introduction

Sampling stage The sampling stage contain two units: Xampling sampling card. Expand. 4X62.5 Mhz digital 12X20.8 Mhz digital Xampling A/D 62.5 Mhz (250 1:4 decim.) Expand 1:3 Analog in ariel Introduction

CTF module Goal : Detects the Support of x(t) and forwards it to DSP unit. Triggered by : Initiation. SCD interrupt. Based on the OMP (Orthogonal Matching Pursuit) algorithm. ariel Introduction

DSP module Goal: Reconstructs the signal from the samples. The unit receives the samples from the memory (latency fifo), matrix A from the memory, and signal support from the CTF unit. The support and samples are coordinated by the latency fifo. The unit performs pseudo-inverse of matrix A (calculates As) using the signal support, that is received from the CTF. Finally the unit multiplies the delayed signal with matrix As. ariel Introduction

SCD module Goal: Detects a change of the signal support. The unit uses the signal energy to decide if the CTF needs to recalculate the signal support. ariel Introduction

Learning Process Composed of 2 independent processes : Algorithm : System main concept. Sampling stage (Xampling and Expand). CTF module. DSP module. LabView : LabView main concepts. FPGA under LabView. Integration. Implementing basic units. Reading matrix from file to memory on FlexRio FPGA using LabView environment. ariel Learning Process

LabView LabView is a System design platform and development environment for a visual programming. LabView allows simple integration of several FPGAs together and simple control of the FPGAs using Host VI including importing / exporting file to / from the system. ariel Environment

LabView There are two options of using VHDL in LabView VIs : CLIP node. IP integration node. ariel Environment

LabView CLIP Node ariel Environment

LabView CLIP Node method ariel Environment

LabView ariel IP Integration Node Environment

LabView – Host VI Environment ariel 3 FPGAs Writes to FPGA   ariel Writes to FPGA (Clip method) Environment

LabView – Target VI ariel Reads from Host VI Environment

LabView Problems Does not support array implementation in VHDL. Does not support our packages when using VHDL. Very long compilation process. LabVIEW software tools don't support multi-core or even multi-thread processes. LabVIEW does not allow stage separation (compilation, elaboration, synthesizing, rout & map) in order to isolate or at least to save time. Lack of debug tools. There is no access to the inner signals in the FPGA. ChipScope/JTag is not supported (see JTag-issues) Lack of tutorials that show usage of VHDL in LabVIEW. genady Environment

LabView Problems genady Environment

LabView Problems genady Environment

LabView Problems genady Environment

JTag / ChipScope JTag is not supported under LabView environment! A critical issue because we cannot debug our design in the real hardware. ariel Environment

Signal’s sample (from memory) Block Diagram DSP Pseudo Inverse Multiplication Signal’s sample (from memory) Matrix A (from memory) Signal support (from CTF) Reconstructed signal As+ A1 A2 genady Hardware

Pseudo-Inverse Diagram Matrix Inverse R matrix R_inv QR Dec Pinv(As) As Q matrix Mat Mult Interface genady Hardware

Implemented Blocks QR-Decomposition. Matrix Multiplier Interface. This blocks are Xilinx-oriented. genady Hardware

Xilinx Synthesis While we were trying to convert Altera oriented code to Xilinx one, we unfortunately discovered that Altera’s synthesis is much stronger and also more efficient than the Xilinx one. Code that includes complicated loops (implementing muxes) cannot be synthesized at all. genady Hardware

Xilinx Synthesis genady Hardware

Part B Blocks Matrix Inverse – upper triangular matrix inverter. Real Time Multiplier. SCD (Signal Change Detector). genady Hardware

Verification Methods Small Blocks Verification via Full DSP Block. After a block is changed from Altera to Xilinx, a full ModelSim simulation is executed. Furthermore, the block is burned on the FPGA using LabView in order to confirm LabView compatibility and time constrains. both System

Verification Methods We verify that Matrix A is inverted correctly using Matlab. both System

Full System Integration Full system integration will be executed during Part B. Once we confirm that all the Xilinx oriented units work well with LabView, we will replace all the relevant mathscript blocks with real hardware ones. both System

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