ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS 4/24/2017 ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS Design for Testability (DFT) - 1

Overview Definition Ad-hoc methods Scan design Summary Design rules Scan register Scan flip-flops Scan test sequences Overhead Scan design system Summary 4/24/2017

Definition Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits: Ad-hoc methods Structured methods: Scan Partial Scan Built-in self-test (BIST) Boundary scan 4/24/2017

Ad-Hoc DFT Methods Good design practices learned through experience are used as guidelines: Don’t-s and Do-s Avoid asynchronous (unclocked) feedback. Avoid delay dependant logic. Avoid parallel drivers. Avoid monostables and self-resetting logic. Avoid gated clocks. Avoid redundant gates. Avoid high fanin fanout combinations. 4/24/2017

Ad-Hoc DFT Methods Good design practices learnt through experience are used as guidelines: Don’t-s and Do-s (contd.) Make flip-flops initializable. Separate digital and analog circuits. Provide test control for difficult-to-control signals. Buses can be useful and make life easier. Limit gate fanin and fanout. Consider ATE requirements (tristates, etc.) 4/24/2017

Ad-Hoc DFT Methods Design reviews Manual analysis Conducted by experts. Programmed analysis Using design auditing tools Programmed enforcement Must use certain design practices and cell types. Objective: Adherence to design guidelines and testability improvement techniques. 4/24/2017

Ad-Hoc DFT Methods Disadvantages of ad-hoc DFT methods: Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary. 4/24/2017

Scan Design Objectives Simple read/write access to all or subset of storage elements in a design. Direct control of storage elements to an arbitrary value (0 or 1). Direct observation of the state of storage elements and hence the internal state of the circuit. Key is – Enhanced controllability and observability. 4/24/2017

Scan Design Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design: Add one (or more) test control (TC) primary input. Replace flip-flops by scan flip-flops and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO. Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test. 4/24/2017

Scan Design Rules Use only clocked D-type flip-flops for all state variables. At least one PI pin must be available for test; more pins, if available, can be used. All clocks must be controlled from PIs. Clocks must not feed data inputs of flip-flops. 4/24/2017

Correcting a Rule Violation All clocks must be controlled from PIs. Comb. logic D1 Q FF Comb. logic D2 CK Comb. logic Q D1 Comb. logic D2 FF CK 4/24/2017

Scan Flip-Flop (master-slave) D Master latch Slave latch TC Q Logic overhead MUX Q SD CK D flip-flop Master open CK Slave open t Normal mode, D selected Scan mode, SD selected TC t 4/24/2017

Level-Sensitive Scan-Design Latch (LSSD) Master latch Slave latch D Q MCK Q SCK D flip-flop SD MCK Normal mode Logic overhead TCK MCK TCK Scan mode TCK SCK t 4/24/2017

Adding Scan Structure PI PO SFF SCANOUT Combinational logic SFF SFF TC or TCK Not shown: CK or MCK/SCK feed all SFFs (scan Flip-flops). SCANIN 4/24/2017

Comb. Test Vectors I1 I2 O1 O2 PI PO Combinational logic SCANIN TC SCANOUT S1 S2 N1 N2 Next state Present state 4/24/2017

Comb. Test Vectors I1 I2 Don’t care or random bits PI SCANIN S1 S2 TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 O1 O2 PO SCANOUT N1 N2 Sequence length = (nsff + 1) ncomb + nsff clock periods ncomb = number of combinational vectors nsff = number of scan flip-flops 4/24/2017

Testing Scan Register Scan register must be tested prior to application of scan test sequences. A shift sequence 00110011 . . . of length nsff+4 in scan mode (TC=0) produces 00, 01, 11 and 10 transitions in all flip-flops and observes the result at SCANOUT output. Total scan test length: ((nsff + 1) ncomb + nsff ) + (nsff + 4) clock periods. (ncomb + 2) nsff + ncomb + 4 clock periods. Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106 clocks. Multiple scan registers reduce test length. 4/24/2017

Multiple Scan Registers Scan flip-flops can be distributed among any number of shift registers, each having a separate scanin and scanout pin. Test sequence length is determined by the longest scan shift register. Just one test control (TC) pin is essential. PI/SCANIN PO/ SCANOUT Combinational logic M U X SFF SFF SFF TC CK 4/24/2017

Scan Overhead IO pins: One pin necessary. Area overhead: Gate overhead = [4 nsff/(ng+10nff)] x 100%, where ng = comb. gates; nff = flip-flops; Example – ng = 100k gates, nff = 2k flip-flops, overhead = 6.7%. More accurate estimate must consider scan wiring and layout area. Performance overhead: Multiplexer delay added in combinational path; approx. two gate-delays. Flip-flop output loading due to one additional fanout; approx. 5-6%. 4/24/2017

Hierarchical Scan Scan flip-flops are chained within subnetworks before chaining subnetworks. Advantages: Automatic scan insertion in netlist Circuit hierarchy preserved – helps in debugging and design changes Disadvantage: Non-optimum chip layout. Scanin Scanout SFF1 SFF4 SFF1 SFF3 Scanin Scanout SFF2 SFF3 SFF4 SFF2 Hierarchical netlist Flat layout 4/24/2017

Optimum Scan Layout X’ X SFF cell IO pad SCANIN Flip- flop cell Y Y’ TC SCAN OUT Routing channels Active areas: XY and X’Y’ Interconnects 4/24/2017

Scan Area Overhead Linear dimensions of active area: X = (C + S) / r X’ = (C + S + aS) / r Y’ = Y + ry = Y + Y(1--b) / T Area overhead X’Y’--XY = -------------- x 100% XY 1--b = [(1+as)(1+ -------) – 1] x 100% T = (as + ------- ) x 100% y = track dimension, wire width+separation C = total comb. cell width S = total non-scan FF cell width s = fractional FF cell area = S/(C+S) a = SFF cell width fractional increase r = number of cell rows or routing channels b = routing fraction in active area T = cell height in track dimension y 4/24/2017

Example: Scan Layout 2,000-gate CMOS chip Fractional area under flip-flop cells, s = 0.478 Scan flip-flop (SFF) cell width increase, a = 0.25 Routing area fraction, b = 0.471 Cell height in routing tracks, T = 10 Calculated overhead = 17.24% Actual measured data: Scan implementation Area overhead Normalized clock rate ______________________________________________________________________ None 0.0 1.00 Hierarchical 16.93% 0.87 Optimum layout 11.90% 0.91 4/24/2017

ATPG Example: S5378 Original 2,781 179 0.0% 4,603 35/49 70.0% 70.9% 0.0% 4,603 35/49 70.0% 70.9% 414 Full-scan 2,781 179 15.66% 4,603 214/228 99.1% 100.0% 585 105,662 Number of combinational gates Number of non-scan flip-flops (10 gates each) Number of scan flip-flops (14 gates each) Gate overhead Number of faults PI/PO for ATPG Fault coverage Fault efficiency Number of ATPG vectors Scan sequence length 4/24/2017

Design and verification Automated Scan Design Behavior, RTL, and logic Design and verification Rule violations Scan design rule audits Gate-level netlist Combinational ATPG Scan hardware insertion Combinational vectors Scan netlist Scan sequence and test program generation Chip layout: Scan- chain optimization, timing verification Scan chain order Design and test data for manufacturing Test program Mask data 4/24/2017

Timing and Power Small delays in scan path and clock skew can cause race condition. Large delays in scan path require slower scan clock. Dynamic multiplexers: Skew between TC and TC signals can cause momentary shorting of D and SD inputs. Random signal activity in combinational circuit during scan can cause excessive power dissipation. 4/24/2017

Summary Scan is the most popular DFT technique: Advantages: Rule-based design Automated DFT hardware insertion Combinational ATPG Advantages: Design automation High fault coverage; helpful in diagnosis Hierarchical – scan-testable modules are easily combined into large scan-testable systems Moderate area (~10%) and speed (~5%) overhead Disadvantages: Large test data volume and long test time Basically a slow speed (DC) test 4/24/2017