1. HIGH-SPEED VLSI TESTING WITH SLOW TEST EQUIPMENT Vishwani D. Agrawal Agere Systems Processor Architectures and Compilers Research Murray Hill, NJ 07974 va@agere.com http://cm.bell-labs.com/cm/cs/who/va June 5, 2001

2. 2CAS Lab Seminar MY RESEARCH  Delay Test High-speed test False path removal: A method of identifying and removing non- functional paths; improves speed and testability; may add hardware (Gharaybeh, Agrawal, Bushnell and Parodi, JETTA-2000) Path-delay fault (PDF) simulator (SPDF): A non-enumerative algorithm implemented at ERC (Parodi, Agrawal, Bushnell, and Wu, ITC’1998), US Patent 6,131,181 (2000)  Design for Testability (DFT) and Test Generation A combinational automatic test pattern generation (ATPG) method for partial-scan circuits (Kim, Agrawal and Saluja, ITC’2001)  High-level test Register-transfer level (RTL) fault modeling using stratified fault sampling (Thaker, Agrawal and Zaghloul, ITC’2000)  Low-Power Design A linear-programming method to determine gate delays for elimination of glitches; US Patent 5,983,007 (1999)  Spectral Methods for Testing On-going research with Rutgers University

3. June 5, 20013CAS Lab Seminar MEANING OF DELAY TEST Combinational logic Transient region Clock period Time Inputs Outputs Inputs and outputs synchronized with clock Flip- flop V1 V2

4. June 5, 20014CAS Lab Seminar PROBLEM STATEMENT  Available automatic test equipment (ATE) speed is 100- 200MHz; VLSI chip speed is 0.5-1GHz  No coverage of delay faults is obtained when ATE applies vectors and samples outputs at slow clock rate  A slow ATE can test delay faults in combinational circuits by skewing the output sampling times  Skewed output sampling method tests very few (mostly PI to PO) paths in sequential circuits  Problem: Develop a delay test method for slow ATEs that will give similar path coverage as obtained with an at-speed ATE

5. June 5, 20015CAS Lab Seminar PREVIOUS WORK  BIST (built-in self-test) with externally supplied high-speed clock (hardware overhead, non-functional paths tested)  ATE pin multiplexing (limited vector capability)  Reduced supply voltage, Wagner and McCluskey, ICCAD’85 (may change critical paths, reduce noise margins)  Latch designed to slow the circuit down in test mode, Agrawal and Chakraborty, US Patent 5,606,567 (1997), ITC’95 (needs special hardware, performance penalty)  Fast clocking of flip-flops with slow vector application and slow output sampling, Krstic, Cheng and Chakradhar, VTS’99 (low path coverage)

6. June 5, 20016CAS Lab Seminar A NEW METHOD  Given a vector-set with specific at-speed PDF coverage  Tester generates two clock signals: Test-clock, N times slower than rated chip clock where N = test-speed reduction factor Rated-clock, obtained by multiplexing N skewed test-clocks  (a) Apply vectors at test-clock speed  (b) Apply rated clock to flip-flops  (c) Synchronize output sampling with test-clock, using a skew, s = rated-clock period  Repeat steps (a)-(c) with skew = 2s, 3s, … Ns  Test application time (TAT) = N 2 x (at-speed TAT)

7. June 5, 20017CAS Lab Seminar TEST APPLICATION Primary inputs FF clock Application 1 Application 2 Application 3 Application 4 Test inputs Speed reduction Factor, N = 4 Output monitor strobes

8. June 5, 20018CAS Lab Seminar TESTING FOR FOUR TYPES OF PATHS FF POPI I II III IV Path Types: IPI PO IIFF FF IIIPI FF IVFF PO

9. June 5, 20019CAS Lab Seminar SOME PROPERTIES OF THE METHOD  All types of paths can be tested  Test application time (TAT) = N 2 x (at-speed TAT)  Coverage determined by simulation  Path-specific test generation possible State a State b State c State c’ i1/o1i1/o2 V1=(i1,a) V2=(i1,b) i1/o3 i1/o4 State c’’ i1/o3 Fault detected State d i1/o5 Future detection Non- detection

10. June 5, 200110CAS Lab Seminar SIMULATED PDF COVERAGE 50% PDF Coverage 1 Slowdown factor (N) 40% 30% 20% 10% 234 s510 - 5,000 random vectors s5378- 5,000 random vectors At-speed ATE Slow ATE

11. June 5, 200111CAS Lab Seminar A LAB EXPERIMENT  Device: CD4029B (Texas Instruments) Function: 4 bit binary/decimal presettable up/down counter Package: 16 pin DIP Gate count: 103 Flip-flop count: 12 I/O count: 9/5 Clock frequency: 4MHz @5V  Tests: Fault coverage vectors from Gentest (90 vectors)  Path delay fault simulation for rated-speed operation and for high-speed test (Parodi et al., ITC’99)  Tests performed by C. Parodi and J. David at Holmdel using HP 82000/400MHz ATE

12. June 5, 200112CAS Lab Seminar RESULTS OF CD4029B TEST Three chips tested (A, B, and C) Maximum all-test-pass clock-rate (MHz) Vector application speed reduction factor, N Chips A B C N=1 (At-speed ) N=2 (Half-speed) N=4 (1/4 speed) 4.367 4.167 4.132 3.937 3.922 4.115 4.167 Simulation showed that slow testing perhaps activated paths that are longer than those activated by at-speed testing.

13. June 5, 200113CAS Lab Seminar A VLSI CHIP EXPERIMENT  BSM2 Chip:Boundary Scan Master Version 2 (Higgins and Srinivasan, VTS’00) Agere 0.35 micron CMOS process 65MHz clock @3.3V Gate count: 18,823; Flip-flop count: 1,368; I/O count: 34/34  Production Tests 453,195 vectors, 96% coverage of stuck-at faults 164,578 tested path faults (total 400 million paths) Longest tested paths - 58 gates (longest physical path - 74 gates)  Path delay fault simulation for rated-speed operation (Parodi et al., ITC’99)  Testing planned (2001) A proof of concept exercise for PDT task force committee Don Denburg (AL): Test programming and ATE S. Wu (ERC) and G. Nanda (IDC): PDF simulation and critical path test generation

14. June 5, 200114CAS Lab Seminar CONCLUSIONCONCLUSION  It is possible to obtain same or higher PDF coverage with a slow ATE as with an at-speed ATE A slow test-clock is used for input application and output monitoring A rated-clock signal is applied to flip-flops; a slow ATE can generate fast rated-clock by pin multiplexing Test application time (TAT) increases as square of speed reduction factor (N): TAT = N 2 x V where:V = number of vectors (for variable clock testing, TAT ~ N 2 x V 2 )  Test application time can be reduced by test optimization Use PDF simulation Generate path-specific tests  Proposed method only tests functional paths