Download presentation
Presentation is loading. Please wait.
Published byArabella Greene Modified over 8 years ago
1
TOPIC : Design of Scan Storage Cells UNIT 4 : Design for testability Module 4.3 Scan Architectures and Testing
2
Introduction A scan cell has both normal operation mode and test mode. It is chosen by using a MUX controlled by N/T signal. It can also be done by a two-clock system. The scan cell can be implemented by using many kinds of flip-flops. We will discuss how a scan storage cell (SSC) is built.
3
Basic Unit in SSC To observe the output, it should be stored for some time period. We use a basic D-latch for this purpose. It is the basic unit in many scan storage cells. D-Latch using NAND gates Representation of D-Latch
4
SSC Design A 2-port clocked master slave flip flop is joined with a MUX to form a SSC. Multiplexed Data flip-flop (MD-FF)Representation
5
Contd … MUX is used to select the mode of operation (normal or test) which is controlled by N/T. Master slave flip-flop is used to observe the output. When N/T = 0, normal data enters from port D1. N/T = 1, scan data (test data) enters at port D2. A single clock is used here, some times different clocks can be used for normal mode and scan mode.
6
SSC design with dual clocked flip-flop Instead of using N/T, two clock pulses can be used which are used to switch the circuit to normal and test modes. This is similar to a MUX with two control lines ck1, ck2. ck1 normal system clock, ck2 scan data input clock. 2-port dual clocked flip-flop (2p-FF)Representation
7
Multiplex Data Shift Register Latch(MD-SRL) It consists of latches L1, L2 with a multiplexed input data. Multiplex data shift register latch (MD-SRL)Representation
8
Contd … Since each latch has its own clock, this cell is not a flip- flop. A MUX is used with N/T as the control signal. D1 normal data D2 scan data
9
2 Port Shift Register Latch (2P-SRL) To avoid the delay introduced by the MUX, a new design can be used as shown in figure.
10
Contd … It is the NAND gate equivalent to the shift register latch used in a level sensitive scan design (LSSD) methodology employed by IBM. ^D1 normal data input D2 or Si scan data input CK1 (C) normal system clock CK2 (A) scan data input clock CK3 (B) L2 latch clock CK1, CK2 can be NORed and can be used as clock to L2. 2P-SRL Symbol
Similar presentations
© 2024 SlidePlayer.com Inc.
All rights reserved.