1. Practically Realizing Random Access Scan Anand S. Mudlapur Department of Electrical and Computer Engineering Auburn University, AL 36849 USA

2. 11/15/2005MS Thesis Defence2 Motivation for This Work Serial scan (SS) test sequence lengths and test power consumption are increasing rapidly. –Reduction of test power and test time are complementary objectives in serial scan. Scope of increasing delay fault coverage is limited in serial scan. In spite of the advantages (test time, test volume, test power, and ease of testing for delay faults), random access scan (RAS) is not popular due to high overhead.

3. 11/15/2005MS Thesis Defence3 Outline Introduction to scan based testing –Advantages –Limitations Introduction to RAS Design of a new toggle RAS Flip-Flop Highlight the uniqueness and feasibility of our design due to the reduction of two global signals

4. 11/15/2005MS Thesis Defence4 Outline (contd.) A new scan-out structure Analytical formulation of hardware overhead Algorithm to compact test vectors ATPG targeted for toggle RAS Results on ISCAS Benchmark Circuits Case study on an industrial circuit Conclusion and future work

5. 11/15/2005MS Thesis Defence5 Serial Scan: Most Popular DFT Method Combinational Circuit FF Scan-inScan-out PIPO Test control (TC)

6. 11/15/2005MS Thesis Defence6 Introduction to Serial Scan (contd.) Advantage: Enables application of combinational vectors to sequential circuits Problems: –Clock cycles prohibitive as number of flip-flops increases –Scan-in often performed at a slow scan clock compared to functional clock of the circuit –Scan-in and scan-out cause undesirable circuit activity resulting in excessive power dissipation

7. 11/15/2005MS Thesis Defence7 Test Power and Time of Serial Scan Test power may exceed critical design limits. All flip-flops are controlled and observed although a test may need those operation only on a subset of flip-flops. Example: A circuit with 5,000 Flip-Flops and 10,000 combinational test vectors Total scan cycles = 5,000 × 10,000 + 10,000 + 5,000 50,015,000 ! = 50,015,000 !

8. 11/15/2005MS Thesis Defence8 Solutions for Test Time Problem of Serial Scan Partial scan [Agrawal et. al. 88] provides a trade off between ease of test generation and hardware cost of scan. Test power may still be a concern. Vector compaction [Touba et. al. 00], may cause increased circuit activity resulting in higher power consumption. Cross-Check [Gheewala et. al. 91] was a comprehensive test method for sequential circuits but the technology required dedicated routing layers for test wiring.

9. 11/15/2005MS Thesis Defence9 Cross-Check A grid architecture as shown in the adjoining figure Flip-flops contents read out row-wise Data from the flip- flops fed into a MISR

10. 11/15/2005MS Thesis Defence10 Solutions for Test Power Problems of Serial Scan Test scheduling for SOCs using power constraint [Chou et. al. 91]: Test parallelism reduces, increasing the test time. Slow scan-clock [Chandra et. al. 94]: Test time increases. ATPG based methods [Wang et. al. 94, Kajihara et. al. 02]: Result in lengthy test sequences. Contd.

11. 11/15/2005MS Thesis Defence11 Further Solutions for Test Power (contd.) Modification of the order of scan cells or inserting inversion logic between scan cells after the test generation [Dabholkar et al. 98]; limited effect on test power. Blocking hardware methods: Hold latch, blocking gates; have additional overhead.

12. 11/15/2005MS Thesis Defence12 Delay Testing in Serial Scan Delay testing in serial scan is highly constrained; may result in low fault coverage. Enhanced scan flip-flops can make the application of arbitrary vectors possible. This technique requires a hold-latch connected to each Flip-Flop in addition to a “HOLD” signal routed to every hold latch resulting in increased area overhead and signal delay in the scan path.

13. 11/15/2005MS Thesis Defence13 Delay Testing in Serial Scan Combinational Circuit SFF PIPO HL Scan-out HOLD Scan-in CKTC CKTC CK TC HOLD V1 s-in V2 state scan-in Scan-out V1V2 Test result latched V1 settles

14. 11/15/2005MS Thesis Defence14 Introduction to RAS Random Access Scan (RAS) offers a single solution to the problems faced by serial scan (SS): –Each RAS cell is uniquely addressable for read and write. –RAS addresses both test application time and test power problems simultaneously Previous and current publications on RAS: Ando, COMPCON -80 Wagner, COMPCON -83 Ito, DAC -90 Baik et al., VLSI Design -04, ITC -05, ATS -05, VLSI Design -06 Mudlapur et al., VDAT -05, ITC-05 Disadvantage: High routing overhead – test control, address and scan-in signals must be routed to all flip-flops.

15. 11/15/2005MS Thesis Defence15 Contributions of Present Work Eliminate scan-in signal from circuit by using a new toggling RAS flip-flop. Eliminate test control signal to flip- flops. Provide a new scan-out architecture: –A hierarchical scan-out bus –An option of multi-cycle scan-out

16. 11/15/2005MS Thesis Defence16 Random Access Scan (RAS) During every test, only a subset of all Flip-flops needs to be set and observed for testing the targeted faults Combinational Circuit FF PIPO Scan-out bus bus Decoder AddressInputs Scan-in TC These signals are eliminated in our design

17. 11/15/2005MS Thesis Defence17 Conventional RAS MS Clock Combinational Logic Data Address Decoder Combinational Logic Data Logic Data RAS-FF MUXMUX MUXMUX Address Register Scan-in Mode ACLK

18. 11/15/2005MS Thesis Defence18 New “Toggle” RAS Flip-Flop MS Clock MUXMUX Combinational Logic Data Row Decoder Column Decoder Combinational Logic Data Logic Data To Output BUS Address (log 2 n ff ) y x √n ff Lines RAS-FF 0 1 OutputBUSControl

19. 11/15/2005MS Thesis Defence19 Toggle RAS Flip-Flop Operation FunctionClock Address decoder outputs Row (x)Column (y) Normal DataActive00 Toggle Data Inactive1Active Clock InactiveActive Clock1 Hold Data Inactive10 01 00

20. 11/15/2005MS Thesis Defence20 Toggle Flip-Flop Operation (contd.) RAS FF 1 Unaddressed FFs Addressed FF RAS FF 0 Decoded address lines RAS FF 0 RAS FF 1 x4 y1 y2 y3

21. 11/15/2005MS Thesis Defence21 Macro Level Idea of Signals to RAS-FF x1 x2 x3 x4 y1y2y3y4 RAS FF11 RAS FF14 RAS FF12 RAS FF13 RAS FF11 RAS FF14 RAS FF12 RAS FF13 RAS FF21 RAS FF24 RAS FF22 RAS FF23 RAS FF31 RAS FF32 RAS FF33 RAS FF34 RAS FF41 RAS FF42 RAS FF43 RAS FF44 To Next Level RAS FF22 4-to-1 Scan-out Macrocell

22. 11/15/2005MS Thesis Defence22 Scan-out Macrocell A 4x4 block scan-out data flow and control logic D-FFs may be inserted at the two outputs of macrocell for multi-cycle scan-out. To Next Level Output BUS Control Signal to Next Level BUS Data Bus From 4 RAS FFs { Control From 4 RAS FFs

23. 11/15/2005MS Thesis Defence23 Routing of Decoder Signals in RAS COLUMN DECODER ROWDECODERROWDECODER Flip-Flops Placed on a Grid StructureAddress (log 2 √n ff ) (log 2 √ n ff ) Address

24. 11/15/2005MS Thesis Defence24 Gate Area Overhead Gate area overhead of Serial Scan = Gate area overhead of Random Access Scan = where n ff – Number of Flip-Flops where n ff – Number of Flip-Flops n g – Number of Gates Assumption: D-FF contains 10 logic gates.

25. 11/15/2005MS Thesis Defence25 Gate Area Overhead (Examples) 1. A circuit with 100,000 gates and 5,000 FFs Gate overhead of serial scan = 13.3 % Gate overhead of RAS = 20.0 % (Typical example from an industrial circuit. Details in later slide) 2. A circuit with 500,000 gates and 5,000 FFs Gate overhead of serial scan = 3.6 % Gate overhead of RAS = 5.5 %

26. 11/15/2005MS Thesis Defence26 Overhead in Terms of Transistors Transistor overhead of Serial Scan = Transistor overhead of Random Access Scan = Where n t is number of transistors in comb. logic. D-flip-flop (28 transistors), serial scan FF (28+10) and RAS FF (28+26) were designed in 0.5μ CMOS technologyusing Mentor Graphics Design Architect. technology using Mentor Graphics Design Architect.

27. 11/15/2005MS Thesis Defence27 Algorithm to Compact Test Vectors Obtain the combinational vectors along with good circuit responses and store the results in a stack Find the Flip-Flops where the faults are propagated at each vector While number of vectors > 0 or remaining faults > 0 – Read all Flip-Flops where the faults are detected – Choose the next vector from stack that is at least hamming distance from current Flip-Flop states End While

28. 11/15/2005MS Thesis Defence28 RAS-FF Compaction of Test Vectors Combinational Circuit RAS-FF PIPO Scan-out bus bus Decoder AddressInputs Stack 101 000 010 110 111 100 001 100 000110

29. 11/15/2005MS Thesis Defence29 Test Time

30. 11/15/2005MS Thesis Defence30 Test Power

31. 11/15/2005MS Thesis Defence31 Case Study on an Industrial Circuit A case study on an industry circuit was performed at Texas Instruments India Pvt. Ltd. The preliminary results were as follows: 1.The gate area overhead of RAS for a chip with ~5500 Flip-Flops and ~100,000 NAND equivalent gates was of the order of 18%. 2.4X reduction in test time was estimated. A speed- up of up to 10X was considered possible using ATPG heuristics. 3.Estimated routing and device area overhead of RAS in physical layout was 10.4%.

32. 11/15/2005MS Thesis Defence32 Conclusion New design of a “Toggle” Flip-Flop reduces the RAS routing overhead. Proposed RAS architecture with new FF has several other advantages: –Algorithmic minimization reduces test cycles by 60%. –Power dissipation during test is reduced by 99%. A novel RAS scan-out method presented. For details on “Toggle” Flip-Flop, see Mudlapur et al., VDAT -05.

33. 11/15/2005MS Thesis Defence33 Backup Slides

34. Thank you!