1. A Robust Pulse-triggered Flip-Flop and Enhanced Scan Cell Design
Tarun Soni
Rajesh Kumar
Sunil P. Khatri
Department of Electrical and Computer Engineering,
Texas A&M University, College Station
Good morning everyone, This presentation is on our work – Pulsed Flip Flop and Enhanced scan cell design. This was done in collaberation with Tarun and Dr. Sunil Khatri.

2. Outline Motivation Scan Design At Speed Scan Testing
Launch on Shift (LOS)
Launch on Capture (LOC)
Enhanced Scan Design
Pulse Flip Flops (PFFs)
Our Robust PFF
Our Pulse based Enhanced Scan Flip Flop (PESFF)
Experimental Results
Conclusion
The agenda of my presentation is as follows. First I will discuss the motivation behind our work that I am going to present . then I will briefly describe scan design and at speed testing.
I will go over previous work on pulsed FF. Then I will discuss our proposed PFF and ES Cell design. Finally, I will go over experimental results and conclusion.

3. Motivation
Decreasing process feature sizes increase the probability of defects during the manufacturing process
A single faulty transistor or wire can result in a faulty IC
Testing required to guarantee fault-free products
Design for testability (DFT)
Addresses testing issues during the design stage itself so that testing after implementation becomes easier
Scan design is the most popular DFT methodology used for sequential circuits
As we are moving to advanced technologies, the decrease in feature size increases the probability of faults during the manufacturing process.
A single faulty transistor can result in a faulty IC. Hence testing is essential for fault free products. Design for testability is required to take care
Of testing issues during the design stage so that testing after implementation(?) becomes easier. Scan Design is the most popular methodology used for sequential circuits.

4. Scan Design Replace all selected storage elements with scan cells
Connect scan cells into scan chains
Operated in three modes:
Normal mode
All test signals are turned off (i.e. SE is held low)
Shift mode
To shift data into and out of the scan cells (SE held high)
Capture mode
To capture test response into scan cells (SE is held low) D Q D D Q Q D Q SI 1
CLK SE
CLK
In the next couple of slides I will briefly discuss scan design. In scan design all storage elements are replaced by scan cells. A scan cell has one mux and one DFF.
Depending upon SE signal either D or SI acts as data input for DFF. After replacement scan cells are connected to form scan chains.
Scan design operates in three modes – First normal mode – In this mode all test signals are turned off. In shown scan cell, SE will be low.
Second is Shift mode, In this mode data is shifted in and out of the scan cells.
Third one is Capture mode, In this mode test response is captured into scan cells.

5. Scan design (continued)
SCANIN = 111
Expected Output = 000
CLK D Q0 1
Shift Shift Shift Capture Shift Shift Shift D Q
SCANIN SI
CLK SE D SI SE 1 Q1
Combinational
Logic D Q
SCANOUT
Figure shown on left is a sequential circuit. All the scan cells are connected to form a scan chain.
The figure shown on right is timing diagram for CLK, SE and Outputs of scan cells. Initially circuit operates in normal
Mode. If we want to test the circuit for an input vector, the circuit needs to operate in test mode. This is done by asserting
SE signal. Input vector is applied thorough scan shift in three clock cycles. The response of the circuit is available
at data input of scan cells. To capture the response in scan chian, circuit is operated in normal mode by making SE signal low. Now SE is enabled to shift out the response of circuit from scan chain. Q0 SE
CLK D SI Q1 1 Q2 D Q Q2 SE
SCANOUT
CLK

6. At Speed Scan Testing
Identifies transition delay fault by applying two vectors V1 and V2
V1 is used to initialize internal logic values of the circuit under test
V2 is used to launch transitions into the combinational circuit
Propagated output is captured in the scan chain by the system clock after launching V2
Three ways to perform at speed scan testing
Launch on Shift
Launch on Capture
Enhanced Scan Design
In this slide I will discuss at speed testing. At speed testing is done to identify transition delay fault in a circuit. This is done by applying two vectors. First vector initializes the internal nodes of circuit and second vector launches the transition. The response of the circuit is captured in the scan chain by the system clock. At speed testing
is performed in three ways – LOS, LOC, Enhanced Scan Design. In next couple of slides I will briefly describe these
Three ways.

7. Launch on Shift (LOS) V2 is restricted to a one-bit shift of V1
V2 Launch
Edge
Capture
Edge V1
CLK SE
Launch cycle is
last scan-in cycle
Capture
cycle
Scan-out
cycle
Scan-in
cycle
Scan-in
cycle
Launch on Shift:
Vector V1 is applied to the combinational circuit during scan-in cycles. Now vector2 is launched
with system clock. Notice that SE is still high, It means V2 is one-bit shift of V1. After launch cycle SE is made low, since we want to capture the response of circuit in scan chain which is available at the data input pin of scan cells.
There are two issues with LOS, V2 is restricted to a one-bit shift of V1.
It requires fast SE signal, since SE is made low between launch and capture edge.
V2 is restricted to a one-bit shift of V1
Requires fast scan enable signal

8. Launch on Capture (LOC)
V2 Launch
Edge
Capture
Edge V1
CLK SE
Launch cycle
Capture
cycle
Scan-out
cycle
Scan-in
cycle
Scan-in
cycle
Launch on Capture:
V1 is applied through scan chain. SE is made low before launching the vector V2. This is the main difference between LOS and LOC. In case of LOS, SE was high at launch edge. It means V2 is the response of circuit to V1.
Capture and Scan out cycle are same as LOS.
LOC has one issue, V2 is the response of circuit to V1. We can not apply all possible combinations of V1 and V2.
Infact Xu and others claimed that LOC has lower fault coverage than LOS.
Uses two consecutive functional clocks to launch the transition and capture the output test response
Vector V2 is the response of the circuit under test to vector V1
Lower fault coverage in comparison to LOS [Xu et. al. ‘07]

9. Enhanced Scan Design
Enhanced-scan cell stores two bits of data per input of the circuit under test
Achieved by adding a D latch to a muxed-D scan cell
No restriction on vector V2
High fault coverage but with some area overhead SE SI
CLK
SCAN IN D Q 1 Q
In this slide, I will discuss the third approach for at speed scan testing. Enhanced scan design uses a scan cell which can store two bits of data per input of the circuit under test. This is done by adding a DFF to a muxed-D scan cell.
The main advantage of this approach is that It has no restriction on V2. V1 and V2 are independent.
That is the reason enhanced scan design gives high fault coverage with some area overhead.

10. Our Contribution Design of a robust PFF
Lower area and better timing than previous approaches
Modify this PFF for use in a pulse based enhanced scan flip-flop
Better timing than DFF based ESFF
These are the our contributions. First one is robust PFF which has better timing than previous approaches.
Second one is ESFF which uses the modified version of our PFF. Our ESFF has better timing than DFF based ESFF.

11. Pulsed Flip-flops (PFF)
Consists of a pulse generator and a latch
The pulse is derived from system clock edge
Hence data can arrive even after the clock edge (therefore Tsu may be negative)
Latch
Data D Q
Clk
Pulse
Pulse
Generator
Pulse
Clk
Clk
In next couple of slides, I will briefly describe a PFF and its figure of merit. The figure shown on left is block diagram of a PFF. A PFF consist of a pulse generator circuit and a latch. The latch is transparent when pulse is high.
If we see the timing diagram, the pulse is derived from the clock edge. As a result, data can also arrive after the clock edge and so a PFF can have negative setup time. This enables the PFF circuits to operate at high speed. In next slide we will see how negative setup time improves the performance.
Data

12. Figure of Merit for a Flip-flop
D Q
CLK
Combinational
circuit
Time Period T ≥ Tcq + Tsu + d
where d – delay of the combinational circuit
Tsu – setup time of the flip-flop
Tcq – clock to Q delay of the flip-flop
Since d is circuit-dependent, Tcq + Tsu is the figure of merit for a flip-flop
The minimum clock period at which circuit can operate depends upon clock to Q delay , delay of the combination circuit and setup time of the FF. Since d is circuit dependent, the figure of merit for a FF is sum of Tcq and setup time.
That is the reason negative setup time gives better timing.

13. Previous Work Fast PFF (Venkatraman et al. 2008)
Pulse generation circuit is faster
Static power dissipation when CLK is high
pulseb
pulseb
CLK
pulse D
CLKB
CLK
pulse
Now I will describe previous work on PFF. Fast FF proposed by Venketraman. This work was done by our group. The figure shows the circuits of a pulse generator and a latch. This design makes the rising edge of pulse faster. As we see in the circuit when CLK is Zero , Pulse is zero and internal node is pulled up. As soon as CLK becomes high, Pulse gets high.
The issue with this design is there is static power dissipation whenever CLK is high. This is because internal node is not pulled down to zero.
Pulse generator
Pulsed latch structure

14. Previous Work (continued)
Explicit PFF (Zhao et al. 2002)
Uses dynamic pulse generator circuit and a static latch to achieve good setup time
Layout area is large and also power consumption is high
CLK
pulse Q
CLKB D
Explicit PFF was proposed by Zhao and others. It uses dynamic pulse generator circuit and a static latch to achieve good setup time.
But layout area of this design is large and power consumption is also high.

15. Previous Work (continued)
Improved hybrid latch flip-flop (Goel et al. 2006)
Modified dynamic master stage of Explicit PFF to reduce power consumption
High clock to Q delay
CLK D Q
Goel and others proposed hybrid latch FF. They modified the dynamic master stage of explicit PFF to reduce the power. This design has high clock to Q delay.

16. Proposed PFF Pulse generator Latch pulseb CLKB CLK pulseb pulse D Q
Now I will describe our proposed robust PFF. The figure shown on left is the circuit of the pulse generator. It uses the CLK and delayed version of inverted clock to generate the pulse. As we see in the timing diagram this is the CLKB signal. CLK and CLKB is applied to a nand gate followed by an inverter. So whenever CLK and CLKB is high pulse is generated. Pulsed latch is used to capture data input.
CLK
Latch
CLKB
pulse

17. Pulse based Enhanced Scan Flip-flop (PESFF)SI
CLK
SCAN IN D Q 1 Q D Q
PULSEB
PULSE
SCAN
SCANB
PULSEB
PULSE D
Our robust PFF
SCAN IN SI
PULSEB
PULSE
SEB SE

18. PESFF (continued) V1 V2 SEB SE SEB SCAN SEB PULSE SCANB V2 Launch
Edge
Capture
Edge V1 V1 V2
CLK
PULSE SE
SCAN

19. Experimental Setup Implemented our PFF and PESFF in BPTM 100nm
Compared PFF with existing designs
Fast Robust Pulsed Flop (Venkatraman et al. 2008)
Explicit Flip-Flop (Zhao et al. 2002)
Improved hybrid pulsed Flip-Flop (Goel et al. 2006)
Traditional D Flip-Flop
Compared PESFF with traditional DFF based ESFF
Performed Monte Carlo simulations for all designs listed above
Varied supply voltage, channel length, threshold voltage
3σ = 10% of the nominal value
200 Monte Carlo simulations
To evaluate the performance of our PFF and enhanced scan FF, we used BPTM 100nm model cards for the simulations.
We compared the performance of our PFF with previous work.
We have also performed monte carlo simulations to evaluate the performance of our design against process variations.
For monte carlo simulations V,L,Vt were varied. The 3sigma value of these parameters were taken as 10% of its nominal value. 200 monte carlo simulations were run.

20. Experimental Results - PFF
Flip-flops
Tcq
(ps)
Tsu
Tcq + Tsu
Power
(µW)
Area
(∑ WiLi)
(um2) σ
Proposed
Pulsed FF
134.6
13.8
-78.7
9.2
54.2
8.6
5.8
0.430
Fast
PULSED FF
163.7
23.7
-68.6
10.1
79.1
20.7
6.7
0.510
HYBRID LATCH
117
14.7
-34.4
1.9
82.6
11.8
8.4
0.410
EXPLICIT PULSED FF
120.4
29.3
-54.2
4.5
65.8
7.3
14.6
0.390
Traditional
D-FF
69.9
1.5
21.4
2.5
91.2
8.7
7.6
0.240
This table compares the performance of our PFF with existing designs. The second and third column reports mean and sigma values of Tcq. The highlighted column reports mean and sigma values of setup time.
The highlighted column reports the figure of merit of a FF which is sum of Tcq and setuptime.

21. Experimental Results - PESFF
Pulse generator has been shared among 10 latches to reduce area and power overhead
Enhanced
Scan Flip-flop
Tcq
(ps)
Tsu
Tcq + Tsu
Power
(µW)
Area
(∑ WiLi)
(um2) σ
PESFF
157.7
16.3
-82.6
6.5
75.1
13.4
10.1
0.880
ESFF using traditional DFF
43.1
5.2
43.7
3.6
86.6
5.8
7.5
0.540

22. PESFF D Q
PULSEB
PULSE
SCAN
SCANB
SCAN IN SI
PULSEB
PULSE
SEB SE

23. Conclusion
The performance of our PFF design is better than existing PFF designs
18% better Tcq + Tsu than explicit PFF
14% lower power dissipation than Fast PFF
60% lower standard deviation of Tcq + Tsu compared to Fast PFF
16% lower area in compared to Fast PFF
No earlier PFF based enhanced scan design
14% better Tcq + Tsu than traditional DFF based ESFF
105% area overhead compared to traditional DFF based ESFF
Selective replacement gives considerable coverage improvement with small area overhead
Now I will conclude my talk.

24. Thank You