An accurate and efficient SSO/SSN simulation methodology for 45 nm LPDDR I/O interface Dr. Souvik Mukherjee, Dr. Rajen Murugan (Texas Instruments Inc.) Vinayakam Subramanian, Dr. Ji Zheng (Apache Design Solutions Inc.)

Introduction  Needs:  Memory interface performance validation is becoming increasingly complex  Increasing speeds, design configurations, design cost optimization in die, package, board  Lower supply voltages allow for lower noise margins (due to SSO/SSN, crosstalk, ISI) on I/O performance metrics.  Look-ahead and comprehensive analysis needed during IO placement/package prototyping early analysis, signoff  Challenges:  SSO/SSN analysis is a coupled Signal-Integrity and Power-Integrity problem.  Requires concurrent modeling and simulation of the chip-package-board Signal delivery network (SDN) and power delivery network (PDN).  Combine the varying (and often conflicting) simulation requirements of the SDN and PDN.  Requires a robust and automated environment to seamlessly integrate the system- level model constituents.  Needs to overcome the challenge of computation complexity of traditional simulations using transistor-level model of the I/O circuits. An “ideal” SSO/SSN analysis methodology needs to accurately trade off between accuracy and efficiency of modeling, extraction and simulation flows 2

Proposed I/O Characterization Methodology  An efficient and accurate “system-level” methodology for characterization of LPDDR I/Os has been presented.  The proposed flow leverages the underlying physics of the SSO/SSN to optimize the modeling and simulation of the system-level constituents  System-level silicon measurements on a actual product have been performed to benchmark the accuracy of the proposed flow 3

Sentinel-SSO Methodology (1/2) 4

Sentinel-SSO Methodology (2/2) Aggressor Modeling Methodology 5

Performance benefit from Sentinel-SSO Macromodel  More than 2X performance improvement with negligible loss in accuracy – 5hrs 10mins with full transistor level spice model for all the DDR bank IOs – 2hrs 20mins with Sentinel-SSO Macromodel for all IOs except victim and two aggressors on each side Red : Full Transistor model- based SPICE simulation Blue: Sentinel-SSO macromodel-based simulation 6

Model-to-hardware correlation  Silicon validation platform was set up with the device-memory interface.  Software code was prepared to exercise the memory interface with minimal extraneous SOC activity.  TDR measurements (for passive channel characterization) and link RLGC/S-parameter parasitic model generation  Micro-probing of data/strobe bit waveforms during LPDDR WRITE transactions (under controlled environment)  Noise measurements on Power Distribution network during LPDDR switching activity 7 Block schematic of the hardware setup

TDR Simulation Flow Import of Memory PCB layout in Sentinel-PSI Model reduction, Technology stack- up, port-setup, analysis settings Parasitic extraction and s- parameter model output SPICE analysis with TDR pulse probe locations) on extracted PCB model Overlay with measurement data Import of Memory PCB, intermediate PCB, CHIP PCB layouts in Sentinel- PSI Model reduction, Technology stack- up, port-setup, analysis settings for each PCB Parasitic extractions and s- parameter model outputs SPICE analysis with TDR pulse probe locations) on cascaded PCB models Overlay with measurement data Simulation Flow with only Memory PCB Simulation flow with full CHIP-MEMORY channel Addition of socket models 8

TDR characterization of memory and full channel (CHIP-to-MEMORY ) //i.cmpnet.com/planetanalog/features/Ansoft_flex/Fig4.jpg Depiction of data bit routing (on DDR PCB w/o DDR IC) characterization with TDR setup Red : Simulation Green: Measurement Model-to-hardware correlation Time (ps) Impedance (ohms) TDR methodology 9

SSO-SSN Simulation Flow Import of Memory PCB, intermediate PCB, CHIP PCB layouts in Sentinel-PSI Model reduction, Technology stack- up, port-setup, analysis settings for each PCB Parasitic extractions and coupled SI/PI s-parameter model outputs Addition of socket models Import of package in 3D EM Tool Model reduction, Technology stack-up, port-setup, analysis settings for package Parasitic extractions and coupled SI/PI s-parameter model outputs Output coupled SI/PI s-parameter model of package CHIP database Sentinel-SSO connectivity and simulation framework Sentinel-SSO connectivity and simulation framework O/P waveform, timing data 10

Supply bounce with activity Pk-to-pk noise on VDDS-VSSS is ~230 mV (no MPU activity ) Yellow: DQS2 Cyan: DQ22 Magenta: CLKN/CLKP Green: VDDS-VSSS Measurement waveform capture: DQ22/DQS2/CLK/VDDS- VSSS MHz) 11

Model-to-hardware correlation for data waveform Red : Simulation Green: Measurement Time (ns) Voltage (v) 12

Conclusions 13  - Develop an efficient IO macromodeling capability to analyze system-level SSO/SSN on a high-speed digital memory interface.  Demonstrated on an LPDDR memory interface for a 45nm SoC design.  Established model-to-hardware correlation.  Innovative capability that alleviates the burden of traditional methodologies that are computationally prohibitive.