1. Anasim  -fp Power integrity analyzer/optimizer Bottomline Benefits  -fp  -fp Raj Nair, Anasim Corporation Anasim Q3 2010

2. September 2010Anasim Confidential2 10,000 Inductors + Through abstraction, pi-fp simulates grids of 100x100 bus pairs, or 10,000 inductors or more, and other associated components, without issues typical in spice. Through abstraction, pi-fp simulates grids of 100x100 bus pairs, or 10,000 inductors or more, and other associated components, without issues typical in spice.

3. September 2010Anasim Confidential3 Speed independent of devices Simulation time is determined only by chip area and spatial accuracy desired. Number of wires, circuit blocks, capacitances, etc. do not affect simulation speed. Simulation time is determined only by chip area and spatial accuracy desired. Number of wires, circuit blocks, capacitances, etc. do not affect simulation speed.

4. September 2010Anasim Confidential4 Optimization capability Simulation speed permits resource usage DOE for aspects such as power grid wire width, bus pitch, on-die capacitance requirements, etc., as determined by desired power noise (PI) & operating supply level. Simulation speed permits resource usage DOE for aspects such as power grid wire width, bus pitch, on-die capacitance requirements, etc., as determined by desired power noise (PI) & operating supply level.

5. September 2010Anasim Confidential5 Constraint relaxation pre-synth. Front-end analysis and optimization capability permits relaxation of routing constraints prior to place & route, speeding timing and physical design convergence. Front-end analysis and optimization capability permits relaxation of routing constraints prior to place & route, speeding timing and physical design convergence. Q: What are some of the methodology issues that limit IC layout productivity? A: Having teams with separate front-end and back-end people. You need an automated way to pass constraints for the circuit designer on the front-end to the layout designer on the back-end. Even floorplanning constraints can be set by the circuit designer. From: http://www.chipdesignmag.com/payne/2010/08/12/cadence-virtuoso-update/ http://www.chipdesignmag.com/payne/2010/08/12/cadence-virtuoso-update/

6. September 2010Anasim Confidential6 True Electromagnetic Simulator  -fp captures true on-chip/system noise 9 x 7mm chip 5nF /sq. cm distributed CAP 100mA peak noise pulse of 100ps width Power grid simulation Explicit CAP LENS Pulse noise source Differential noise R+L+C Dynamic Noise Simulation in  -fp Animation slide

7. September 2010Anasim Confidential7 Backup

8. September 2010Anasim Confidential8 Advanced SiP Solutions Analysis Near load systems Near load systems Active Noise Regulator* Active Noise Regulator* Distributed Local Voltage Regulators Distributed Local Voltage Regulators Integrated Solutions Integrated Solutions On-Chip Dynamic Voltage Scaling (DVS) On-Chip Dynamic Voltage Scaling (DVS) Energy Management in Package (EMP) Energy Management in Package (EMP) Stacked power conversion silicon layer Stacked power conversion silicon layer Chip power grid noise ANR attached to top left corner of grid Reference: * Nair & Bennett, ComLSIComLSI Power Management Designline article http://www.powermanagementdesignline.com/howto/175800373http://www.powermanagementdesignline.com/howto/175800373 Intel® CMOS Regulator chip Animation slide