1. Are classical design flows suitable below 0.18  ? ISPD 2001 NEC Electronics Inc. WR0999.ppt-1 Wolfgang Roethig Senior Engineering Manager EDA R&D Group

2. ISPD panel April 2 2001 Slide 2 of 10 Classical Design Approaches Full-custom design hand-craft the design, transistor-level analysis time-consuming methodology, usable only for standard products Low-end ASIC automated design process, huge margin to guarantee functionality fast TAT, yet sub-optimal use of process technology High-end ASIC design must bridge the gap fast TAT through automation, yet more sophisticated tools aggressive design, but still sign-off guarantee

3. ISPD panel April 2 2001 Slide 3 of 10 New ASIC design issues A VDSM design flow must solve all these issues How to calculate and fix timing in the presence of crosstalk and noise? How to check the entire design for localized voltage drops? How to guarantee manufacturability by correct layout? How to ensure reliability against electromigration and hot electron effects? How to partition a complex SOC design into manageable blocks? How to analyze and reduce chip power consumption?

4. ISPD panel April 2 2001 Slide 4 of 10 Example: crosstalk Two signals on adjacent wires switch simultaneously + 20 % @ 0.5 mm + 40 % @ 1 mm double + 0 % @ 1 mm + 10 % @ 3 mm + 30 % @ 0.5 mm + 40 % @ 1 mm double + 10 % @ 1 mm + 30 % @ 3 mm + 70 % @ 0.5 mm + 100 % @ 1 mm single + 10 % @ 1 mm + 60 % @ 3 mm + 70 % @ 0.5 mm + 100 % @ 1 mm single + 40 % @ 1 mm + 90 % @ 3 mm Delay increases up to 100% with single pitch 2x drive aggressor affects even 8x drive victim Delay increases up to 40% even with double pitch Significant effect even for 0.5 mm wire  delay % @ wire length (3rd metal in 0.18u) victim aggressor 2x strength 8x strength 2x strength8x strength routing pitch

5. ISPD panel April 2 2001 Slide 5 of 10 Example: power and current density Power consumption in 0.18  6 times higher than in 0.35  Current density in 0.18  10 times higher than in 0.35  Therefore dramatic increase in electromigration and voltage drop effects max. # gates6 Meg12 Meg34 Meg power / gate / MHz 0.07  W0.04  W0.02  W max. clock frequency120 MHz230 MHz450 MHz Power / Power(0.35  ) 12.26.12 supply voltage3.3 V2.5 V1.8 V Current / Current (0.35  ) 12.911.3 max. numbers are absolute technology limits Technology 0.35  0.25  0.18  power = # gates x frequency x power / gate / MHz current = power / supply voltage

6. ISPD panel April 2 2001 Slide 6 of 10 Reliability and Manufacturability More complicated rules for design tools Technology 0.35  0.25  0.18  0.13  ReliabilityManufacturability No design issue Electromigration & hot electron check for cells Global antenna rules Layer-specific antenna rules Electromigration & hot electron check for cells, avg. current limit Layer-specific antenna rules and metal density rules Electromigration & hot electron check for cells and interconnect, avg. and peak current limit

7. ISPD panel April 2 2001 Slide 7 of 10 Consequences Signal integrity effects can not be handled in isolation –crosstalk is the effect of multiple interacting signals –voltage drop is a system-level effect –reliability and manufacturability rules reduce the degrees of freedom for timing optimization –timing affects xtalk and vice versa –timing affects power and vice versa Design tools need to be signal-integrity literate –coherent and concurrent design and analysis of all signal integrity effects is required –transistor-level analysis is not feasible –need higher level abstract analysis models

8. ISPD panel April 2 2001 Slide 8 of 10 Changing Design Environment RTL Synthesis Gate Placement Routing Timing check Timing check 1998 0.25  2MG 100MHz Gate Physical Synthesis Timing Optimization Physical Synthesis Timing Optimization Routing RTL Synthesis 2000 0.18  Signal Integrity Check&Repair Signal Integrity Check&Repair 10MG 200MHz Gate-level planning 2002 0.13  RTL Planning RTL 30MG 400MHz Physical Synthesis Timing, Power, Signal Integrity Optimization Physical Synthesis Timing, Power, Signal Integrity Optimization Routing Signal Integrity Correctness Routing Signal Integrity Correctness Timing, xtalk, antenna, electromigraqtion Timing, xtalk, antenna, electromigraqtion Power consumption, Voltage drop Power consumption, Voltage drop

9. ISPD panel April 2 2001 Slide 9 of 10 Need for advanced library modeling Design flow will need common or compatible analysis backplane Technology library and its components (cells, blocks, wires) need to be characterized –timing and power are not sufficient –crosstalk delay and noise, electromigration, hot electron effect, manufacturability must be described Models must be –accurate for high performance ICs –efficient for analysis and optimization –suitable for designers (model specification) as well as for characterization, design and analysis tools (model usage) The Advanced Library Format (ALF) provides a solution –Already proliferating in the industry –Emerging IEEE standard (see www.eda.org)

10. ISPD panel April 2 2001 Slide 10 of 10 Conclusion Classical ASIC design flow is changing –increasing complexity: hierarchical design –decreasing geometry: signal integrity VDSM technology requires more aggressive design –not enough room for guard bands: physics are too severe –not enough time for manual work: designs are too large New generation of design tools and flows –concurrent design and analysis for timing, power, signal integrity, manufacturability using advanced library models Merge of design flows –SOC contains ASIC-style blocks and custom blocks –Hierarchical design, analysis and optimization enabled by abstract models of the blocks