Topics Design methodologies. Kitchen timer example.

Design methodologies Every company has its own design methodology. Methodology depends on: size of chip; design time constraints; cost/performance; available tools.

Generic design flow architectural simulation register-transfer logic detailed specs floorplan functional/ performance verification layout circuit design tapeout testability

Specification and planning Driven by contradictory impulses: customer-centric concerns about cost, performance, etc.; forecasts of feasibility of cost and performance. Features, performance, power, etc. may be negotiated at early stages; negotiation at later stages creates problems.

Estimation and planning Estimation techniques vary with module: memories may be generated once size is known; data paths may be estimated from previous design; controllers are hard to estimate without details. Estimates must include speed, area, power.

Floorplanning and budgeting The purpose of early floorplanning is to establish budgets for each major component: area, delay, power, etc. The project leader must ensure that budgets are met at all times. If it becomes clear that meeting a budget for a component is impossible, the floorplan must be redone ASAP.

Logic design For controllers, good state assignment is usually requires CAD tools. Logic synthesis is an option: very good for non-critical logic; can work well for speed-critical logic. Logic synthesis system may be sensitive to changes in the input specification.

Circuit/layout design Tasks: size transistors; draw layout. Alternative design styles: full custom logic (very tedious); standard cell. Full custom most likely for datapaths, least likely for random logic off critical path.

Design validation Must verify: layout (design rule check = DRC); circuit performance; clock distribution; functionality; power consumption / power bussing.

Testing Automatic test pattern generation = ATPG. Must verify that circuit can be tested, generate a compact set of manufacturing test vectors. Test vectors often comprised of vectors taken from simulation + ATPG-generated vectors.

Tapeout Tapeout: generating final files for masks. Shipped to mask-making house. Pre-tapeout verification is importance since it will take months to get results from fab. Tapeout party follows. Size of party depends on importance of chip design project.

Kitchen timer chip Simple example which illustrates overall design process. Kitchen timer keeps two independent timers: set minutes, seconds. go, clear; Not performance-sensitive; is power-sensitive.

Kitchen timer system timer chip seconds timer 1 timer 2 go minutes clear

Timer chip architecture sketch buttons controller enable timer 1 timer 1 display buzz segments buzzer

Functional simulator Given in Appendix C. Operates in event-driven style: seconds clock; button depressions. Provides basic functional verification, allows exercising major architectural components.

Major design decisions Use binary-coded decimal (BCD) to represent times: allows direct display of timer register values; requires a few more registers than binary, but BCD/7-segment decoder is much smaller than binary/7-segment decoder. Use scanned display—send only one digit at a time to display to reduce wiring between components.

Kitchen timer component hierarchy timer chip controller buzz timers display timer 1 timer 2

Component inventory Timers: Holds time in register; can increment, decrement, clear. Inputs: incr_seconds[2], incr_minutes[2], seconds, go[2], digit_select[2], timer. Outputs: done, digit[4]. Display: Cycles through displayed digits. Inputs: digit[4]. Outputs: digit_select[2], enable[4], segments[7].

Component inventory (cont’d) Buzz: Enables buzz signal until stop. Inputs: done, stop. Outputs: buzz. Controller: Generates all required control signals. Inputs: timer_1, timer_2, minutes_in, seconds_in, clear_in, go_in. Outputs: timer_select, incr_minutes, go, clear, output_select.

Component size estimates One timer: 14 latches and about 30 gates. Timers: 28 latches and 70 gates. Display: 4 latches and about 15 gates. Buzz: 2 latches and 2 gates. Controller: 8 latches and 20 gates.

Kitchen timer initial floorplan 4 timers 4 display 7 4 buzz 1 1 controller 4