1. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Topics n Layouts for logic networks. n Channel routing. n Simulation.

2. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Standard cell layout n Layout made of small cells: gates, flip- flops, etc. n Cells are hand-designed. n Assembly of cells is automatic: –cells arranged in rows; –wires routed between (and through) cells.

3. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Standard cell structure VDD VSS n tub p tub Intra-cell wiring pullups pulldowns pin Feedthrough area

4. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Standard cell design n Pitch: height of cell. –All cells have same pitch, may have different widths. n VDD, VSS connections are designed to run through cells. n A feedthrough area may allow wires to be routed over the cell.

5. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Single-row layout design Routing channel cell wireHorizontal track Vertical track height

6. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Routing channels n Tracks form a grid for routing. –Spacing between tracks is center-to-center distance between wires. –Track spacing depends on wire layer used. n Different layers are (generally) used for horizontal and vertical wires. –Horizontal and vertical can be routed relatively independently.

7. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Routing channel design n Placement of cells determines placement of pins. n Pin placement determines difficulty of routing problem. n Density: lower bound on number of horizontal tracks needed to route the channel. –Maximum number of nets crossing from one end of channel to the other.

8. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Pin placement and routing before abc bca abc bca Density = 3 Density = 2

9. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Example: full adder layout n Two outputs: sum, carry. sum carry x1 x2 n1 n2 n3 n4

10. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Layout methodology n Generate candidates, evaluate area and speed. –Can improve candidate without starting from scratch. n To generate a candidate: –place gates in a row; –draw wires between gates and primary inputs/outputs; –measure channel density.

11. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR A candidate layout x1x2n1n2n3n4 a b c s cout Density = 5

12. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Improvement strategies n Swap pairs of gates. –Doesn’t help here. n Exchange larger groups of cells. –Swapping order of sum and carry groups doesn’t help either. n This seems to be the placement that gives the lowest channel density. –Cell sizes are fixed, so channel height determines area.

13. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Left-edge algorithm n Basic channel routing algorithm. n Assumes one horizontal segment per net. n Sweep pins from left to right: –assign horizontal segment to lowest available track.

14. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Example ABC ABBC

15. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Limitations of left-edge algorithm n Some combinations of nets require more than one horizontal segment per net. BA AB aligned ?

16. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Vertical constraints n Aligned pins form vertical constraints. –Wire to lower pin must be on lower track; wire to upper pin must be above lower pin’s wire. BA AB

17. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Dogleg wire n A dogleg wire has more than one horizontal segment. BA AB

18. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Rat’s nest plot n Can be used to judge placement before final routing.

19. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Simulation n Goals of simulation: –functional verification; –timing; –power consumption; –testability.

20. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Types of simulation n Circuit simulation: –analog voltages and currents. n Timing simulation: –simple analog models to provide timing but not detailed waveforms. n Switch simulation: –transistors as semi-ideal switches.

21. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Types of simulation, cont’d. n Gate simulation: –logic gates as primitive elements. n Models for gate simulation: –zero delay; –unit delay; –variable delay. n Fault simulation: –models fault propagation (more later).

22. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Example: switch simulation a + + b c d c 1 0 0 X X X o 0 1 1

23. Modern VLSI Design 3e: Chapter 4 Copyright  1998, 2002 Prentice Hall PTR Example, cont’d. a + + b c d c 1 0 0 0 1 1 o 0 1 0 0