1. Topics
Architecture of FPGA:
Logic elements.
Interconnect.
Pins.

2. Architectural issues How many logic elements in the FPGA?
LE structure:
What functions?
How many inputs?
Dedicated logic?
What types of interconnect?
How much of each type?
How long should interconnect segments be?
How should we vary interconnect?
Uniform or non-uniform over chip?

3. FPGA architecture evaluation methodology
fabric
architecture
Logic
benchmarks
Place +
route
Area and
performance
evaluation
metrics

4. Evaluation metrics Structural: Mapping-related:
Size of the logic element.
Size of interconnect.
Mapping-related:
Logic utilization.
Interconnect utilization.
Delay.

5. Logic element parameters
How many inputs?
Too few inputs---more overhead per LE.
Too many inputs---wasted capacity when mapping logic to LEs.
Depends on circuit design of LE and characteristics of logic.
Typical choice: 4-inputs.

6. LE clusters Logic elements + dedicated interconnect.
Less-than-full connectivity between cluster inputs and LEs.
Smaller than maximal LE. l LE n i
Local
routing l LE

7. Logic cluster utilization (Betz & Rose)
Logic utilization vs. fraction of inputs accessible to LE in cluster.
Utilization at 100% when only 50%-60% of inputs are accessible.
Also found that connecting each track to only one LE output per cluster was sufficient.
© 1998 IEEE

8. Area efficiency vs. cluster size (Betz & Rose)
Transistors per LE vs. cluster size.
Includes overhead circuits.
Clusters in size 1-8 were area-efficient.
© 1998 IEEE

9. Styles of FPGA interconnect
Local.
Intermediate.
Global:
clock;
signal.

10. Interconnect paths LE
channel SW
channel LE
channel SW
channel

11. Intermediate wiring channels
A wire runs for L logic blocks: LE LE LE LE
switch
L=1
switch
L=3
switch
L=4

12. Wiring connection structure
Connects to 3 other wires at each endpoint.
Connects to 1 other wire at channel crossing.
Can be driven by one output pin. LE LE LE LE

13. Routing segment length vs. delay (Brown et al)
Y axis: percentage of length 2 tracks.
X axis: percentage of length 3 tracks.
Remaining tracks are of length 1.
Sweet spot with majority of tracks length 3.
© 1996 IEEE

14. Track distribution (Betz & Rose)
Is wiring concentrated near the center of the FPGA?
No.
Is wiring directional (horizontal/vertical)?
Make channels to I/O pins about 25% larger.

15. Pinout How many pins? Limited by technology.
Too much logic, not enough pins means we can’t get signals off-chip.
Too many pins means logic won’t be fully utilized.

16. Rent’s Rule Developed by E. F. Rent (IBM) in 1960.
Experimentally derived from sample designs.
Number of pins vs. number of components is a line on a log-log plot:
Np = Kp Nsb
Parameters may vary based on technology:
Rent measured b = 0.6, Kp = 2.5.
Modern microprocessor has b = 0.455, Kp = 0.82.

17. FPGAs and pins
Chip capacity is growing somewhat faster than package pinout.
Harder to use logic in a multi-FPGA design.
Must try to fit a large function with a small interface into the FPGA.