Unit 11 Latches and Flip-Flops Fundamentals of Logic Design By Roth and Kinney

11.1 Introduction Sequential circuits—have the property that the output depends not only on the present input but also on the past sequence of inputs. Latch--a memory element that has no clock input. Flip-flop—a memory device that changes its output in response to a clock input and not in response to a data input.

11.1 (cont.) Feedback—the output of one of the gates is connected back into the input of another gate in the circuit. Stable states or conditions—see figure

11.2 Set-Reset Latch Simple Latch—feedback is introduced into a simple NOR circuit. See figures 11-3(a,b) and 11-4(a,b) –S=R=0—a stable condition can exist with P=1 and Q =0. –S=1; R=0– circuit state changes to Q = 1. –S=0; R=0—circuit state remains as Q=1. –S=0;R= 1—circuit state can change to Q=0; Note that S=R=1 is not allowed. Note also that P=Q’.

11.2 Figure 11-5 illustrates the “cross-coupled” form. S is for SET and R is for RESET –Q = 1 for SET –Q = 0 for RESET

11.2 (cont.) Concepts –Present state –Next State Q + –Present output Table 11-1—S-R Latch Next State and Output Figure 11-8 Derivation of Next state for an S-R Latch

11.2 (cont.) Using NANDS for an S’-R’ Latch –See Figure (page 342)

11.3 Gated Latches Gated Latches have an additional input— the enable or gate input. –See Figure –Gated D Latch is shown in Figure

11.4 Edge-Triggered D Flip-Flop See Figure –Rising Edge Trigger (change occurs on rising edge of the clock.) –Falling Edge Trigger –Truth Table and Characteristic (state) Equation Timing (see Figure 11-18). Fig illustrates the set up (tsu) time and the hold time (th).

11.5 S-R Flip-Flop The S-R FF is similar to a latch, except now there is a clock. The Master-Slave Implementation is shown in Figure (p.349)

11.6 J-K Flip-Flop An extended version of the S-R FF; inputs: –J (corresponds to S) –K (corresponds to R) –Clock Figure illustrates the J-K FF.

11.7 T Flip-Flop Toggle FF—often used to build counters. –T input (T=0 means no toggle; T=1 means toggle. –Clock input Figure 11-26, page 351 Figure 11-27, page 352 Figure 11-28, page 352, implementations.

11.8 Flip-Flops with Additional Inputs Additional Inputs can be used to initialize FFs. Figure 11-29—Clear and Preset. Figure 11-31—illustrates enable.

11.9 Asynchronous Sequential Circuits Asynchronous Sequential Circuits—state can change when input changes.

11.10 Summary Characteristic Equations –Page 357 S-R latch or FF Gated D latch D FF –Page 358 D-CE FF J-K FF T FF