MICAS Department of Electrical Engineering (ESAT) Design-In for EMC on digital circuit December 5th, 2005 Low Emission Digital Circuit Design Junfeng Zhou Wim Dehaene KULeuven ESAT-MICAS

MICAS Department of Electrical Engineering (ESAT) Outline 1. Introduction 2. Logic family selection 3. Clock strategy selection SSCG - Delay cell array approach 4. Low noise power supply

MICAS Department of Electrical Engineering (ESAT) Part I: Introduction Electro-Magnetic Interference (EMI) and radiated emission have become a major problem for high speed digital circuit, Most of them are due to power and ground fluctuation. Although the detailed calculation of EMI noise is rather difficult, we can use the di/dt as the index, since the current loop contributes the EMI.

MICAS Department of Electrical Engineering (ESAT) Part 2: Logic Family Selection SCMOS PNMOSRSBCMOS CSL MCMLFSCL

MICAS Department of Electrical Engineering (ESAT) Comparison of di/dt,power and area Target : Mixed-Mode Automotive Electronics Design Key aspects : di/dt + Power + Area + Speed Ring Oscillator of 21-stages (Static + Dynamic) Current Steering Logic But there is static power !!

MICAS Department of Electrical Engineering (ESAT) Detailed comparison of CSL and SCMOS Note: The curve of CSL 16-bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I. CSL One-bit Adder IT is a static power problem, Switching off when standby ?

MICAS Department of Electrical Engineering (ESAT) Detailed comparison of CSL and SCMOS SCMOS CSL

MICAS Department of Electrical Engineering (ESAT) Problem with CSL Mismatch sensitive, annoying for standard cells rather slow/power hungry Not full swing Matching required! M1 > M3

MICAS Department of Electrical Engineering (ESAT) Can we do it better ? C-CBL: sizing for optimal current balance is really difficult,process dependent CBL [Albuquerque, E.F.M.; Silva, M.M., Current-balanced logic for mixed-signal IC's]

MICAS Department of Electrical Engineering (ESAT) Solution- Enhanced current steering logic Still current source basing Increase in logic level, hence increase the robustness Reduced output capacitance, hence the speed is increased Fig.3 E-CSL inverter Minimum size

MICAS Department of Electrical Engineering (ESAT) Comparison of CSL, C-CBL, ECSL and SCMOS Fig.5 di/dt vs. frequencyFig.4 power vs. frequency Ring Oscillator of 21-stages

MICAS Department of Electrical Engineering (ESAT) di/dt performance vs. process variation Fig.6 di/dt vs. process corner MAX di/dt change MIN di/dt change Ring Oscillator of 21-stages

MICAS Department of Electrical Engineering (ESAT) Conclusion of Low noise Logic Families Winner is E-CSL CSL,E-CSL show a smaller area per logic function for complex digital gates and systems compared to SCMOS logic technique. Current source ensures the major di/dt reduction, Process variation sensitivity also becomes better due to the dominance of current source, E-CSL gives comparable di/dt performance with CSL, E-CSL is Faster and Less power consuming than CSL due to the lower area and lower capacitance. Static power consumption remains the challenge for wide application of the CSL,E-CSL technique in very large digital systems. Can be solved by using power down strategies, which is highly application dependent

MICAS Department of Electrical Engineering (ESAT) Part II: Clock strategy (SSCG) [Keith B. Hardin, Spread Spectrum Clock Generation for the Reduction of Radiated Emissions] 1. Deviating the period of the clock signal from its fundamental by a small percentage(usually +/- 1% ) and in a predictable fashion(usually Triangular modulation profile ) 2. The total power of the clock signal remains the same. Implementation: 1. PLL-SSCG: VCO has its input voltage controlled by a modulation waveform. 2. DCA-SSCG: By controlling the temporal spacing of the edges, the clock ’ s frequency is indirectly controlled

MICAS Department of Electrical Engineering (ESAT) SSCG - PLL vs. DCA ? Disadvantage of PLL-SSCG: Basically analog circuit(VCO, charge pump, loop filter), more susceptible to noise PLL-SSCG suffers from the drawback of reduction in maximum achievable EMI reduction due to the inherent random jitter of the circuitry(due to thermal noise, flicker noise). Leads to large jitter in clock which is unacceptable Advantage of DCA-SSCG Digital circuits, good immunity to noise. Leads to smaller random jitter, simpler implementation and reduction in area The reduction in variance of unintentional jitter is key to the delay cell array technique being able to achieve greater reduction in EMI.

MICAS Department of Electrical Engineering (ESAT) SSCG-DCA : How does it work ? Each delay cell comprised of delay element and a positive latch: EN DQ DQ DQ … Delay Cell #1Delay Cell #2Delay Cell #N Result: Edge-to-edge jitter varied in deterministic fashion. f0f0 SSC: f 0 + ∆f N/2 Counter Q T T Flip-Flop Delay Cell Control

MICAS Department of Electrical Engineering (ESAT) Clock Attenuation Our results show: Dominant power in odd harmonics DCA-SSCG:  Delay cell based SSCG implemented shows low power and simple circuit implementation  8dB of clock attenuation on fundamental  Improved design can be achieved by using differential delay cell element

MICAS Department of Electrical Engineering (ESAT) Part III: Low Noise Power supply design However 2 problems still remain: Static power consumption New logic family standard cell must be designed and characterised ?? Is there any global approach ??

MICAS Department of Electrical Engineering (ESAT) Questions Thank you for your attention