1. Towards a Fully Digital State-of-the-art Analog SiPM
Andrada Muntean1, Esteban Venialgo1, Salvatore Gnecchi2, Carl Jackson2, Edoardo Charbon3
1Delft University of Technology, Delft, The Netherlands,
2SensL, Cork, Ireland
3EPFL, Lausanne, Switzerland

2. Outline
Goal and Objectives
Architecture
Results
Conclusions

3. Silicon Photomultipliers
Analog SiPM
Digital SiPM

4. Why SiPM? Compact Low bias voltage Insensitive to magnetic fields
Noise characteristics improved through manufacturing processes
Low cost
Low power consumption
Good timing resolution

5. SiPMs (2) Analog SiPM with FAST output Ĩ = ĩ1 +ĩ2 +ĩ3 +ĩ4 + … + ĩnv1 + C
FAST
OUTPUT
STANDARD
OUTPUT

6. Fast Output SensL
Source: SensL

7. TDC Goal of this work Analog SiPM with digital output
FAST
OUTPUT
TDC
DIGITAL
OUTPUT
STANDARD
OUTPUT
Analog SiPM with digital output
Backward-compatible

8. Objectives Reduction of internal parasitics Digital output
Versatility / simplicity
Compactness

9. Architecture FAST STANDARD OUTPUT Ring Oscillator MSB START Vref LSB
STOP

10. Multi-Path ring oscillator
Source: A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping
(Matthew Z. Straayer, Michael H. Perrott)

11. TDC – doubling RO frequency
Counter
Tri-state delay cells
Small area
No calibration

12. Tri-state three inputs inverter
Quicker transition for each input
Faster oscillation period
Minimum dimensions
Symmetric inverter

13. TDC – phase recycling Count=1 D-FF Φ0 Φ1 Φ2 Φ3 Φ4 Φ5 Φ6 Φ7 Φ8 STOP 8 7Φ0 Φ1 Φ2 Φ3 Φ4 Φ5 Φ6 Φ7 Φ8
STOP
D-FF 1 8 7 6 5 4 3 2
Count=1

14. TDC – phase recycling Count=1 D-FF Φ0 Φ1 Φ2 Φ3 Φ4 Φ5 Φ6 Φ7 Φ8 STOP 8 7Φ0 Φ1 Φ2 Φ3 Φ4 Φ5 Φ6 Φ7 Φ8
STOP
D-FF 1 8 7 6 5 4 3 2
Count=1

15. TDC – phase recycling Count=1 D-FF Φ0 Φ1 Φ2 Φ3 Φ4 Φ5 Φ6 Φ7 Φ8 STOP 8 7Φ0 Φ1 Φ2 Φ3 Φ4 Φ5 Φ6 Φ7 Φ8
STOP
D-FF 1 8 7 6 5 4 3 2
Count=1

16. Advantages & Drawbacks
Simplicity
Fast oscillation period with only 9 delay stages
Good LSB
Smaller area compared to other TDC architectures
Complex layout (symmetric delay lines)

17. TDC layout TDC area: 73.67µm x 363.35µm -> 26767µm2 COUNTER VCO
SERIALIZER
TDC area: 73.67µm x µm -> 26767µm2

18. Results – TDC performance (no anti-phase)
TT LSB =64.49ps
FS LSB = 67.95ps
SF LSB = 69.39ps
FF LSB = 45.71ps
SS LSB = 91.79ps
Performance
Value
LSB
64.49 ps (TT)
DNL
+/ LSB (TT)
INL
+/- 1.0 LSB (TT)
Worst-case DNL
+1.28/-1 LSB
Worst-case INL
+2.12/-1.66 LSB

19. Results – PVT sensitivity
LSB vs. Temperature
LSB vs. Vdd RING

20. System performance summary
Value
SiPM
420nm
51 % FF
75 %
DCR
50 kcps/mm2
TDC
LSB (std/anti-phase)
64.5/35 ps
DNL/INL (TT)
+/ /-1.0 LSB
Resolution
10 bits
Supply
3.3 V
Input
Single-ended
Readout clock
40 MHz
Power (peak / standby)
<9mW / <1mW
System
Area
3 x 3.3 mm2
Backward-compatible
yes
3 mm

21. Conclusions
Expected improvement of parasitics in a fully integrated solution
Backward-compatibility guaranteed
Simplicity and compactness

22. Current and future work
Develop new TDC architectures
Low complexity, robust, scalable, versatile
Increase timestamping granularity (more/faster TDCs)
3D ICs will enable the combination of SiPM optimized technologies with advanced CMOS low-power processes

23. Acknowledgements The Swiss National Science Foundation
SensL for funding, in part, this research and for providing technology support