® Spartan-II High Volume Solutions Overview

® High Performance System Features Software and Cores Smallest Die Size Lowest Possible Cost Low Cost Plastic Packages Streamlined Testing Xilinx Spartan Series FPGAs

® 100,000 gates for $10 Pricing for 250,000 units, end-2000, slowest speed, cheapest package Spartan-II Expands the Spartan Series  Expands ASIC market coverage over Spartan-XL —2-3X gates per I/O pin, 5X total gates —2X gates per dollar —2X I/O performance  Integrates more system functions —DLLs, FIFOs, translators, bus interfaces (PCI)  Fast, predictable routing performance and easy-to- use design flows

® 40K $10 Spartan-XL Spartan-II System Gates Spartan-III 30K 250K 100K FIFOs PALs HDLC UARTs 32-bit, 33- MHz PCI PCI-MIPS Bridge 64 Bit PCI Reed Solomon Encoder ATM IMA Graphics Card Office Networking Set-Top Box Embedded uP Apps Video Line Buffer Cable Modem Ethernet MAC Pricing for 250,000 units, slowest speed, cheapest package, indicated timeframe Higher Density Enables New Applications

® K 175K 150K 125K 100K 75K 50K 25K 0 I/Os System Gates XCS30/XL XCS20/XL XCS05/XL XCS40/XL ASICs & Spartan FPGAs Gates vs. I/Os XCS10/XL Spartan-II FPGAs Gate Arrays Spartan/XL XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200

® Reprogrammability is the Advantage Advantages over ASICs  Time to Market advantage —First to market increases revenue yield  Time in Market advantage —Increases the revenue yield while in field

® Spartan-II  Low Cost  Low Power  Density (15K to 200K)  High VolumeSpartan-II  Low Cost  Low Power  Density (15K to 200K)  High Volume Virtex-E  High I/O  Performance  Density (50K to 3.2M)  System integration Virtex-E  High I/O  Performance  Density (50K to 3.2M)  System integration Architecture FPGA Focus Products CY00

® Spartan-II Product Matrix

® -5 Spartan-XL Spartan-II -4 Speed Virtex Spartan-II Speed Grades  Strategy —Fast enough for high volume applications —Simplify speed grade offering  Implementation —Spartan-II offers -5 & -6

® DLL CL IOB IOBIOB IOBIOB IOBIOB IOBIOB DLL CL... CLB RAMRAM RAMRAM RAMRAM RAMRAM I/O Routing Ring True Dual-Port TM 4K bit RAM Clock management Multiply clock Divide clock De-skew clock Chip to Backplane PCI 33MHz 3.3V PCI 33MHz 5.0V PCI 66MHz 3.3V GTL, GTL+, AGP Chip to Memory HSTL-I, HSTL-III HSTL-IV SSTL3-I, SSTL3-II SSTL2-I, SSTL2-II CTT Chip to Chip LVTTL, LVCMOS SelectI/O TM Technology Logic and Distributed RAM Configurable Logic Block (CLB) Delay Locked Loop (DLL) 4Kx1 2Kx2 1Kx4 512x8 256x16 Block Memory Spartan-II Architecture

® 2ns CLB Array High Performance Routing  Routing delay depends primarily on distance —Direction independent —Device-size independent  Predictable for early design analysis  Critical for cores

® $ Spartan-XL Spartan-II Graphics Add-In Card Office Networking Set-Top Box xDSL Modems 200 MHz Memory Continuum - Transparent Bandwidth Cable Modems Internet Devices DSP Coefficients Small FIFOs 16x1 Distributed RAM Large FIFOs Video Line Buffers Cache Tag Memory 4Kx1 2Kx2 1Kx4 512x8 256x16 Block RAM SDRAM SGRAM PB SRAM DDR SRAM ZBT SRAM QDR SRAM External RAM Pricing for 250,000 units, slowest speed, cheapest package, indicated timeframe Block RAM Enables New Applications

® RAMB4_S4_S16 WEB ENB RSTB CLKB ADDRB[7:0] DIB[15:0] WEA ENA RSTA CLKA ADDRA[9:0] DIA[3:0] DOA[3:0] DOB[15:0] Spartan-II True Dual-Port Block RAM Port A Port B W R W R W R R W Data Flow Spartan-II A to B Yes B to A Yes A to A Yes B to B Yes Spartan-II Block RAM  True dual-port static RAM - 4K bits —Independently configurable port data width –4K x 1; 2K x 2; 1K x 4; 512 x 8; 256 x 16 —Fast synchronous read and write –2.5ns clock-to-output with 1.0ns input address/data setup

® DLL1 DLL2 DLL3 DLL4 Deskew clocks on chip Manage up to 4 system clocks Deskew clocks on board Cascade DLLs Generate clocks multiply divide shift Convert clock levels using SelectI/O Delay Locked Loops lower memory and board costs Spartan-II Clock Management

® Spartan-II SelectI/O 3 Types of I/O Interfaces SDRAM SSTL GTL+ LVTTL LVCMOS HSTL SRAM PCI Chip to Memory SSTL2-I, SSTL2-II, SSTL3-I, SSTL3-II, HSTL-I, HSTL-III, HSTL-IV, CTT Chip to Backplane PCI33-5V, PCI33-3.3V, GTL, GTL+, AGP Chip to Chip LVTTL, LVCMOS, 5-volt tolerant

® I/O Standards Summary

® I/O Performance Using SelectI/O & DLL Technology

® Spartan-II Core Support  BaseBLOX basic functions —Arithmetic (adders, counters, multipliers, etcetera) —Memory (single port, dual port, FIFO, etcetera)  AllianceCORE support —Microprocessor peripherals —Microcontrollers —Memory controllers (SDRAM) —Communications –ATM, Ethernet, error correction (Reed-Solomon, Viterbi), telecom (HDLC), etc.

® Spartan-II PCI LogiCORE Solutions  PCI32/33 —XC2S30/50/100/150-5 PQ208 –Pre-release version based on advance speed files  PCI64/33 —XC2S100/150-6 FG456  New PCI back-end design - in development —PLX-like, including DMA, FIFOs, and interrupt control  PCI-X Support - under evaluation

® GTL+ 5-volt tolerant I/O SDRAM QDR SRAMs MIPS uP 2x CLK PCI PLL $7.50 PCI Master/ Target Controller $15 SSTL-3 Translators $4 FIFOs Dual Ports $7$2 $40 $6 GTL+ Backplane Drivers HSTL Translators $6 Spartan-II: System Integration PCI-MIPS System Controller SSTL3 Clock Mgmt - Board deskew Memory

® DLLs Delay Locked Loops SelectI/O Technology Memory Distributed + Block External 100,000 Gates for $10 Reprogrammable ASIC Replacement! Pricing for 250,000 units, end-2000, slowest speed, cheapest package Spartan-II: The Total Solution

® Reprogrammability at ASIC prices Spartan-II Summary  Expand ASIC market coverage for Spartan Series —More gates per I/O and more gates per dollar —Higher density and performance —New features: Block RAM, DLL, SelectI/O technology  Optimized for low cost  Software support in 2.1i with latest service pack