Penn ESE370 Fall Townley & DeHon ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: October 5, 2011 Layout and Area

2 Today Layout –Transistors –Gates Design rules Standard cells Penn ESE370 Fall Townley & DeHon

3 Transistor Side view Perspective view Penn ESE370 Fall Townley & DeHon

4 Layout Sizing & positioning of transistors Designer controls W,L t ox fixed for process –Sometimes thick/thin oxide “flavors” Penn ESE370 Fall Townley & DeHon

5 NMOS Geometry Top viewPerspective view L W Penn ESE370 Fall Townley & DeHon

6 NMOS Geometry Top view L W Color scheme –Red: gate –Green: source and drain areas (n type diffusion) SDG Penn ESE370 Fall Townley & DeHon

7 t ox Transistors built by depositing materials –Constant rate of deposition (nm/min) –Time controls t ox Oxides across entire chip deposited at same time –Same time interval –thickness is (roughly) constant –Process engineer sets value to: Assure yield What does t ox control? –Field strength  V th, current –Achieve Performance, minimize leakage Penn ESE370 Fall Townley & DeHon

8 NMOS vs PMOS Rabaey text, Fig 2.1 Penn ESE370 Fall Townley & DeHon Mostly talked about NMOS so far –PMOS: “opposite” in some sense –NMOS built on p substrate, PMOS built on n substrate –Name refers to bias/carriers when channel is inverted

9 PMOS Geometry n well L W Color scheme –Red: gate –Orange: source and drain areas (p type) –Green: n well NMOS built on p wafer –Must add n material to build PMOS SDG Penn ESE370 Fall Townley & DeHon

10 Body Contact “Fourth terminal” Needed to set voltage around device –PMOS: V b = V dd –NMOS: V b = GND At right: PMOS (orange) with body contact (dark green) Penn ESE370 Fall Townley & DeHon

From: Rotate All but PMOS Transistor 90 degrees

12 Interconnect How to connect transistors –Different layers of metal Intermediate layers “Contact” - metal to transistor “Via” - metal to metal Rabaey text, Fig 2.7k Penn ESE370 Fall Townley & DeHon

13 Interconnect Cross Section ITRS 2007 Penn ESE370 Fall Townley & DeHon

14 Masks Define areas want to see in layer –Think of “stencil” for material deposition Use photoresist (PR) to form the “stencil” –Expose PR through mask –PR dissolves in exposed area –Material is deposited Only “sticks” in area w/ dissolved PR Penn ESE370 Fall Townley & DeHon

15 Masking Process Goal: draw a shape on the substrate –Simplest example: draw a rectangle Silicon wafer Mask Penn ESE370 Fall Townley & DeHon

16 Masking Process First: deposit photoresist photoresist Mask Silicon wafer Penn ESE370 Fall Townley & DeHon

17 Masking Process Expose through mask –UV light Penn ESE370 Fall Townley & DeHon

18 Masking Process Remove mask and develop PR –Exposed area dissolves –This is “positive photoresist” Penn ESE370 Fall Townley & DeHon

19 Masking Process Deposit metal through PR window –Then dissolve remaining PR Why not just use mask? –Masks are expensive –Shine light through mask to etch PR –Can reuse mask Penn ESE370 Fall Townley & DeHon

20 Logic Gates How to build compete inverter? –Connect NMOS, PMOS using metal HW4, part 6: reverse engineer layouts into gates Penn ESE370 Fall Townley & DeHon

21 Inverter Layout Example Penn ESE370 Fall Townley & DeHon

22 Inverter Layout Example Start with PMOS, NMOS transistors Space for interconnect Penn ESE370 Fall Townley & DeHon

23 Inverter Layout Example Penn ESE370 Fall Townley & DeHon

24 Inverter Layout Example Add body contacts Connect gates of transistors Penn ESE370 Fall Townley & DeHon

25 Inverter Layout Example Penn ESE370 Fall Townley & DeHon

26 Inverter Layout Example Add contacts to source, drain, gate, body Connect using metal (blue) Penn ESE370 Fall Townley & DeHon

27 Design Rules Why not adjacent transistors? –Plenty of empty space –If area is money, pack in as much as possible Recall: processing imprecise –Margin of error for process variation Penn ESE370 Fall Townley & DeHon

28 Design Rules Contract between process engineer & designer –Minimum width/spacing –Can be (often are) process specific Lambda rules: scalable design rules –In terms of = 0.5 L min (L drawn ) –Can migrate designs from similar process –Limited scope: 45nm process != 1  m Penn ESE370 Fall Townley & DeHon

Design Rules: Some Examples Penn ESE370 Fall Townley & DeHon n doping p doping gate contact metal 1 metal 2 via Legend

30 Layout Revisited How to “decode” circuit from layout? Penn ESE370 Fall Townley & DeHon

Penn ESE370 Fall DeHon 31 Layout to Circuit 1. Identify transistors Penn ESE370 Fall Townley & DeHon

32 Layout to Circuit 2. Add wires Penn ESE370 Fall Townley & DeHon

33 Layout to Circuit 2. Add wires Penn ESE370 Fall Townley (DeHon)Penn ESE370 Fall Townley & DeHon

34 Layout to Circuit 2. Add wires Penn ESE370 Fall Townley (DeHon)Penn ESE370 Fall Townley & DeHon

35 Layout to Circuit 2. Add wires Penn ESE370 Fall Townley (DeHon)Penn ESE370 Fall Townley & DeHon

36 Layout #2 (practice) Penn ESE370 Fall Townley & DeHon

37 Layout #2 (practice) How many transistors? –PMOS? –NMOS? How connected? –PMOS, NMOS? Inputs connected? Outputs? What is it? Penn ESE370 Fall Townley & DeHon

38 Standard Cells Lay out gates so that heights match –Rows of adjacent cells –Standardized sizes Motivation: automated place and route –EDA tools convert HDL to layout Penn ESE370 Fall Townley & DeHon

Standard Cell Area invnand3 All cells uniform height Width of channel determined by routing Cell area Identify the full custom and standard cell regions on 386DX die

Admin HW4 due Friday Exam next Wednesday –No class at noon that day Penn ESE370 Fall Townley & DeHon

Exam Function from CMOS circuit CMOS circuit to implement function Restoration / Noise Margins –Potentially including MOS equations –Might include variation CMOS gate switching delay Penn ESE370 Fall Townley & DeHon

42 Big Idea Layouts are physical realization of circuit –Geometry tradeoff Can decrease spacing at the cost of yield Design rules Can go from circuit to layout or layout to circuit by inspection Penn ESE370 Fall Townley & DeHon