Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 27: November 14, 2011 Memory Core

Today 6T SRAM review 5T SRAM –Charge sharing –Precharge DRAM Leakage Multiport SRAM (time permitting) Penn ESE370 Fall DeHon 2

Memory Bank Penn ESE370 Fall DeHon 3

4 SRAM Memory bit

Memory Bank Penn ESE370 Fall DeHon 5

5T SRAM Penn ESE370 Fall DeHon 6

Consider What happens to voltage at A when WL turns from 0  1? –Assume W access large –W access >> W pu =1 –BL initially 0 –A initially 1 Penn ESE370 Fall DeHon 7

Voltage After enable Word Line Q BL = 0 Q A = (1V)(  (2+W access )C 0 ) C BL >>C A =(  (2+W access )C 0 ) After enable W access (W access large) –Total charge Q BL +Q A roughly unchanged –Distributed over larger capacitance~=C BL –V A =V BL ~= C A /C BL Penn ESE370 Fall DeHon 8

Larger Resistance? What happens if W access small? –W access < W pu Penn ESE370 Fall DeHon 9

Larger Resistance? What happens if W access small? –W access < W pu Takes time to move charge from A to BL Moves more slowly than replished by pu Penn ESE370 Fall DeHon 10

Simulation: W access =100 Penn ESE370 Fall DeHon 11

Simulation Penn ESE370 Fall DeHon 12

Charge Sharing Conclude: charge sharing can pull down voltage Penn ESE370 Fall DeHon 13

Consider What happens to voltage at A when WL turns from 0  1? –Assume W access large Penn ESE370 Fall DeHon 14

Simulation W access =20 Penn ESE370 Fall DeHon 15

Simulation W access =4 Penn ESE370 Fall DeHon 16

Charge Sharing Conclude: charge sharing can lead to read upset –Charge redistribution adequate to flip state of bit Penn ESE370 Fall DeHon 17

How might we avoid? Penn ESE370 Fall DeHon 18

Charge to middle Voltage Charge bitlines to V dd /2 before begin read operation Now charge sharing doesn’t swing to opposite side of midpoint Penn ESE370 Fall DeHon 19

Pre-Charge Use one phase of clock to charge a node to some initial value before operation Penn ESE370 Fall DeHon 20 Precharge Transistor Can be large

Simulation W access =20 Penn ESE370 Fall DeHon 21

Compare Both W access =20; vary precharge Penn ESE370 Fall DeHon 22

5T SRAM Questions? Similar charge issues for 6T Precharge is equalizing the bit lines Penn ESE370 Fall DeHon 23

DRAM Penn ESE370 Fall DeHon 24

1T 1C DRAM Simplest case – Memory is capacitor –Feature of DRAM process is ability to make large capacitor compactly Penn ESE370 Fall DeHon 25

1T DRAM What happens when read this cell? Penn ESE370 Fall DeHon 26

1T DRAM On read, charge sharing –V BL = (C bit /C BL )V store Small swing on bit line –Must be able to detect –Means want large C bit limit bits/bitline so V BL large enough Cell always depleted on read –Must be rewritten Penn ESE370 Fall DeHon 27

Penn ESE370 Fall DeHon 28 Dynamic RAM Takes sharing idea one step further Share refresh/restoration logic as well Only left with access transistor and capacitor

3T DRAM Penn ESE370 Fall DeHon 29

3T DRAM How does this work? –Write? –Read? Penn ESE370 Fall DeHon 30

3T DRAM Correct operation not sensitive to sizing Does not deplete cell on read No charge sharing with stored state All NMOS (single well) Prechage ReadData Must use V dd +V TN on W to write full voltage Penn ESE370 Fall DeHon 31

Penn ESE370 Fall DeHon 32 Some Numbers (memory) Register as stand-alone element (14T)  4K 2 Static RAM cell (6T)  1K 2 –SRAM Memory (single ported) Dynamic RAM cell (DRAM process)  Dynamic RAM cell (SRAM process)  300 2

Energy Penn ESE370 Fall DeHon 33

Single Port Memory What fraction is involved in a read/write? What are most cells doing on a cycle? Reads are slow –Cycles long  lots of time to leak Penn ESE370 Fall DeHon 34

ITRS nm Penn ESE370 Fall DeHon 35 High Performance Low Power I sd,leak 100nA/  m50pA/  m I sd,sat 1200  A/  m560  A/  m C g,total 1fF/  m0.91fF/  m V th 285mV585mV C 0 =  m × C g,total

High Power Process V=1V d=1000  =0.5 W access =W buf =2 Full swing for simplicity C sc = 0 –(just for simplicity, typically <C load ) BL: C load =1000C 0 ≈ 45 fF = 45× F W N = 2  I leak = 9×10 -9 A P= (45× ) freq ×9×10 -9 W Penn ESE370 Fall DeHon 36

Relative Power P= (45× ) freq ×9×10 -9 W P= (4.5× ) freq + 9×10 -6 W Crossover freq<200MHz How partial swing on bit line change?  Reduce dynamic energy  Increase percentage in leakage energy  Reduce crossover frequency Penn ESE370 Fall DeHon 37

Consequence Leakage energy can dominate in large memories Care about low operating (or stand-by) power Use process or transistors with high V th –Reduce leakage at expense of speed Penn ESE370 Fall DeHon 38

Multiport RAM Skip to admin Penn ESE370 Fall DeHon 39

Mulitport Perform multiple operations simultaneously –E.g. Processor register file R3  R1+R2 Requires two reads and one write Penn ESE370 Fall DeHon 40

Simple Idea Add access transistors to 5T Penn ESE370 Fall DeHon 41

Watch? What do we need to be careful about? Penn ESE370 Fall DeHon 42

Adding Write Port Penn ESE370 Fall DeHon 43

Write Port What options does this raise? Penn ESE370 Fall DeHon 44

Opportunity Asymmetric cell size Separate sizing constraints –Weak drive into write port (W restore ) –Strong drive into read port (W buf ) Penn ESE370 Fall DeHon 45

Isolate BL form Mem Penn ESE370 Fall DeHon 46 Larger, but more robust Essential for large # of read ports Precharge ReadData High

Multiple Write Ports Penn ESE370 Fall DeHon 47

Admin Get started on Project 2 –Timing constraints for correct operation –Select and size your memory cell Tuesday -- André away—no office hours Lectures Wednesday and Friday as usual –Finish up memories on Wednesday Penn ESE370 Fall DeHon 48

Idea Memory can be compact Rich design space Demands careful sizing Penn ESE370 Fall DeHon 49