1. Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 19: October 19, 2012 Ratioed Logic

2. Previously Restoration and Noise Margins CMOS Gates –Drive rail-to-rail –Only one transistor turned on in steady state Only subthreshold current in steady state Penn ESE370 Fall2012 -- DeHon 2

3. Today Ratioed Gates –Correctness –Performance –Power –Implications Penn ESE370 Fall2012 -- DeHon 3

4. Note on what about to see Not clear win Should be able to analyze –Chance to exercise analysis –Kind of thing you want to be able to analyze Pattern should recognize Stepping stone to more interesting things to come… Penn ESE370 Fall2012 -- DeHon 4

5. Idea Building both pull-up and pull-down can be expensive – many gates Seems wasteful to build logic function twice –Once in pullup, once in pulldown –Large capacitance Penn ESE370 Fall2012 -- DeHon 5

6. Idea Maybe only need to build one Build NFET pulldown –Exploit high N mobility traditional Penn ESE370 Fall2012 -- DeHon 6

7. Ratioed Inverter Does this work? –Vout for Vin=0V ? –Vout for Vin=1V ? Penn ESE370 Fall2012 -- DeHon 7 W P =1 WN=1WN=1

8. Ratioed Inverter Does this work? –Vout for Vin=0V ? –Vout for Vin=1V ? Penn ESE370 Fall2012 -- DeHon 8 W P =1 WN=1WN=1

9. Ratioed Inverter Wn=1 Penn ESE370 Fall2012 -- DeHon 9

10. Ratioed Inverter How do we need to size N to make it work? Penn ESE370 Fall2012 -- DeHon 10 W P =1

11. DC Transfer Function Penn ESE370 Fall2012 -- DeHon 11

12. Ratioed Inverter How do we need to size P to make it work? Penn ESE370 Fall2012 -- DeHon 12 W N =1

13. P vs. N Conclude: still prefer N to P for ratioed logic –….at least for now Penn ESE370 Fall2012 -- DeHon 13

14. Worst-Case Output Drive Strength? R drive ? Penn ESE370 Fall2012 -- DeHon 14 W P =1

15. Noise Margin Tradeoff What is impact of increasing (reducing) noise margin? Penn ESE370 Fall2012 -- DeHon 15

16. Ratioed Inverter Sizing Penn ESE370 Fall2012 -- DeHon 16

17. Ratioed Inverter Sizing What causes knee in curve at high end? Penn ESE370 Fall2012 -- DeHon 17

18. Size for R 0 /2 drive? How do we size for R 0 /2 drive? Penn ESE370 Fall2012 -- DeHon 18

19. Compare Static CMOS For R drive =R 0 /2 inverter Total Transistor Width? Input capacitance load? Penn ESE370 Fall2012 -- DeHon 19

20. Power? I static ? Output high? –I leak Output low? –I pmos_on –V dd /(R 0 /2) -- for our sample case Penn ESE370 Fall2012 -- DeHon 20

21. Power P tot ≈ a(½C load +C sc )V 2 f +P low V 2 /R pon +(1-P low )VI ’ s (W/L)e -Vt/(nkT/q) Penn ESE370 Fall2012 -- DeHon 21

22. How size for R 0 /2 drive? Penn ESE370 Fall2012 -- DeHon 22

23. How size for R 0 /2 drive? Penn ESE370 Fall2012 -- DeHon 23

24. Which Implementation is faster in ratioed logic? Penn ESE370 Fall2012 -- DeHon 24

25. Illustrates Preferred gate changes Penn ESE370 Fall2012 -- DeHon 25

26. How size for R 0 /2 drive? How size K-input nor? Penn ESE370 Fall2012 -- DeHon 26

27. When better than CMOS nor-k? Better = smaller, lower input capacitance Penn ESE370 Fall2012 -- DeHon 27

28. Energy vs. Power? Which do we care about? –Battery operated devices? –Desktops? –Pay for energy by kW-Hr? Penn ESE370 Fall2012 -- DeHon 28

29. Admin Penn Fall Break on Monday and Tuesday Project –Should have read it –Built and simulated baseline over weekend –Start list of optimizations to try If don’t have list by Wed, talk with Udit Penn ESE370 Fall2012 -- DeHon 29

30. Ideas There are other logic disciplines We have the tools to analyze Ratioed Logic –Tradeoff noise margin for Reduced area? Capacitive load? –Dissipates static power in one mode Penn ESE370 Fall2012 -- DeHon 30