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Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 2: August 29, 2014 Transistor Introduction.

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Presentation on theme: "Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 2: August 29, 2014 Transistor Introduction."— Presentation transcript:

1 Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 2: August 29, 2014 Transistor Introduction

2 Today MOSFET Capacitive and resistive loads Zero-th order transistor model –Good enough for [what?] Diagnostic Quiz (12:40pm) Penn ESE370 Fall2014 -- DeHon 2

3 MOSFET Metal Oxide Semiconductor Field Effect Transistor –New device –Primary active component for the term –Three terminal device Voltage at gate controls conduction between two other terminals (source, drain) Penn ESE370 Fall2014 -- DeHon 3

4 MOSFET Ids vs. Vgs, Vds Penn ESE370 Fall2014 -- DeHon 4 I DS Vgs = Vg-VsVds = Vd-Vs

5 MOSFET I vs. Vgs, Vds Will dig into understanding during term Today: simple ways to reason about gross behavior –Static/DC Penn ESE370 Fall2014 -- DeHon 5

6 Preclass What voltage do the cases converge to? Penn ESE370 Fall2014 -- DeHon 6

7 Final Voltage? Penn ESE370 Fall2014 -- DeHon 7

8 Final Voltage? Penn ESE370 Fall2014 -- DeHon 8

9 Final Voltage? Penn ESE370 Fall2014 -- DeHon 9

10 Final Voltage? Penn ESE370 Fall2014 -- DeHon 10

11 Conclude? DC/Steady-State –Ignore the capacitors –Look like “open circuit” Penn ESE370 Fall2014 -- DeHon 11

12 Quasistatic Static – inputs (and circuit) unchanging, how does it settle? Dynamic – what happens when things change Quasi-Static – inputs transition, circuit responds, and settles –Dynamic transition to roughly static states Penn ESE370 Fall2014 -- DeHon 12

13 Quasistatic Relevance? How relevant to a combinational digital circuit? How relevant to a clocked digital circuit? Penn ESE370 Fall2014 -- DeHon 13

14 Zero-th Order MOSFET Ideal Switch Vgs > Vth  conducts Vgs < Vth  does not conduct Vth – threshold voltage Gate draws no current from input –Loads input capacitively Penn ESE370 Fall2014 -- DeHon 14

15 Zero-th Order MOSFET Penn ESE370 Fall2014 -- DeHon 15 I DS Vgs = Vg-Vs

16 N-Type, P-Type MOSFET N – negative carriers –electrons Switch turned on positive Vgs P – positive carriers –holes Switch turned on negative Vgs Penn ESE370 Fall2014 -- DeHon 16 Vthp<0 Vgs<Vthp to to conduct

17 Electrons and Holes Penn ESE370 Fall2014 -- DeHon 17

18 Symmetry Device is symmetric Doesn’t know source from drain Think of it as a resistor: –Also doesn’t know difference between two ends –Which way does current flow? N-type: –Electrons are carriers –Electrons charged? negative –Electrons flow from src  drain –From which voltage? Lowest voltage  highest –Drain is ? most positive terminal Penn ESE370 Fall2014 -- DeHon 18

19 Symmetry Device is symmetric Doesn’t know source from drain Think of it as a resistor: –Which way does current flow? P-type: –Holes are carriers –Holes charged how? positively –Holes flow from src  drain –From which voltage? Highest voltage  lowest –Drain is? most negative terminal Penn ESE370 Fall2014 -- DeHon 19

20 Zero-th Order MOSFET Penn ESE370 Fall2014 -- DeHon 20 I DS

21 Why zero-order useful? Penn ESE370 Fall2014 -- DeHon 21 Note S, D annotation on this slide (won’t be labeled in future) Why is it this way?

22 What happens when Vin=Vdd>Vthn Penn ESE370 Fall2014 -- DeHon 22 Vthp=-Vthn Vgs = Vg-Vs

23 What happens when Vin=Vdd>Vth Penn ESE370 Fall2014 -- DeHon 23 Vgs=Vg-Vs=Vdd > Vthn Vthp=-Vthn

24 What happens when Vin=Vdd>Vth Penn ESE370 Fall2014 -- DeHon 24 Vgs=Vdd > Vth Vthp=-Vthn

25 What happens when Vin=Vdd>Vth Penn ESE370 Fall2014 -- DeHon 25 Vgs=Vdd > Vth Vgs=0 > Vthp Vthp=-Vthn

26 What happens when Vin=Vdd>Vth Penn ESE370 Fall2014 -- DeHon 26 Vgs=Vdd > Vthn Vgs=0 > Vthp Vthp=-Vthn

27 What happens when Vin=Vdd>Vth Penn ESE370 Fall2014 -- DeHon 27 Vgs=Vdd > Vthn Vgs=0 > Vthp V2=Gnd Vthp=-Vthn

28 What happens when Vin=Vdd>Vth Penn ESE370 Fall2014 -- DeHon 28 Vgs=Vdd > Vthn Vgs=0 > Vthp V2=Gnd Vgs=0 < Vthn Vthp=-Vthn

29 What happens when Vin=Vdd>Vth Penn ESE370 Fall2014 -- DeHon 29 Vgs=Vdd > Vthn Vgs=0 > Vthp V2=Gnd Vgs=0 < Vthn Vthp=-Vthn Vgs=-Vdd < Vthp

30 What happens when Vin=Vdd>Vth Penn ESE370 Fall2014 -- DeHon 30 Vgs=Vdd > Vthn Vgs=0 > Vthp V2=Gnd Vgs=0 < Vthn Vgs=-Vdd < Vthp Vout=Vdd Vthp=-Vthn

31 What happens when Vin=0<Vth Penn ESE370 Fall2014 -- DeHon 31 Work on board

32 What happens when Vin=0<Vth Penn ESE370 Fall2014 -- DeHon 32 V2=Vdd Vout=0

33 What function? Buffer Vin=Vdd  Vout=Vdd Vin=0  Vout=0 Penn ESE370 Fall2014 -- DeHon 33

34 Why Zeroth Order Useful? Allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits Make sure understand logical function (achieve logical function) before worrying about performance details Penn ESE370 Fall2014 -- DeHon 34

35 Why adequate? Static analysis – can ignore capacitors Capacitive loads – resistances don’t matter Feed forward for gates – –don’t generally have loops –can work forward from known values Logic drive to voltage rails (rail-to-rail) –Don’t have to reason about intermediate voltage levels Penn ESE370 Fall2014 -- DeHon 35

36 What not tell us? Delay Dynamics Behavior if not –Capacitively loaded –Acyclic (if there are Loops) –Rail-to-rail drive Penn ESE370 Fall2014 -- DeHon 36

37 Big Ideas MOSFET Transistor as switch Purpose-driven simplified modeling –Aid reasoning –Sanity check –Simplify design Penn ESE370 Fall2014 -- DeHon 37

38 Admin HW1 out –Can reason through pr 1 from today’s lecture –Try to work over weekend Monday holiday: Labor Day Office Hours –Prof. (Levine 270) T 4:15-5:30pm –(poll for TA office hours on Wed.) Advice Reminder: Should be thinking about this course every day. Penn ESE370 Fall2014 -- DeHon 38

39 Diagnostic Quiz Turnin Quiz and feedback before leaving (do not turnin preclass  keep that) Penn ESE370 Fall2014 -- DeHon 39

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