SEMINAR PRESENTATION ON IC FABRICATION PROCESS

Slides:

Advertisements

Similar presentations

FABRICATION PROCESSES

Advertisements

Course: Analog Circuit Design Time schedule: Tu We Th Office hours: Tu Exams: Feb. (2), Jun.-Jul. (2), Sep.

Process Flow : Overhead and Cross Section Views ( Diagrams courtesy of Mr. Bryant Colwill ) Grey=Si, Blue=Silicon Dioxide, Red=Photoresist, Purple= Phosphorus.

CMOS Fabrication EMT 251.

Lecture 0: Introduction

Simplified Example of a LOCOS Fabrication Process

CMOS Process at a Glance

Wally Dream Job.

VLSI Design Lecture 2: Basic Fabrication Steps and Layout

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.

1 Microelectronics Processing Course - J. Salzman - Jan Microelectronics Processing Oxidation.

Fabrication of p-n junction in Si Silicon wafer [1-0-0] Type: N Dopant: P Resistivity: Ω-cm Thickness: µm.

Introduction to CMOS VLSI Design Lecture 0: Introduction

Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.

Microelectronics & Device Fabrication. Vacuum Tube Devices Thermionic valve Two (di) Electrodes (ode)

The Physical Structure (NMOS)

Design and Implementation of VLSI Systems (EN0160) Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Sedra/Prentice Hall, Saint/McGrawHill,

Lecture #51 Lecture #5 – VLSI Design Review zPhotolithography zPatterning Silicon zProcess steps used are: yStarts with Si wafer yThermal oxidation yPhotoresist.

The Deposition Process

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #5.

Device Fabrication Example

Introduction Integrated circuits: many transistors on one chip.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process I Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.

Rochester Institute of Technology - MicroE © REP/LFF 8/17/2015 Metal Gate PMOS Process EMCR201 PMOS page-1  10 Micrometer Design Rules  4 Design Layers.

ISAT 436 Micro-/Nanofabrication and Applications MOS Transistor Fabrication David J. Lawrence Spring 2001.

Z. Feng VLSI Design 1.1 VLSI Design MOSFET Zhuo Feng.

Manufacturing Process

Solid State Electronics

Micro-fabrication.

CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.

Fabrication of Active Matrix (STEM) Detectors

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #2. Chip Fabrication  Silicon Ingots  Wafers  Chip Fabrication Steps (FEOL, BEOL)  Processing Categories 

Outline Introduction CMOS devices CMOS technology

Lecture 0: Introduction. CMOS VLSI Design 4th Ed. 0: Introduction2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale.

1. A clean single crystal silicon (Si) wafer which is doped n-type (ColumnV elements of the periodic table). MOS devices are typically fabricated on a,

SEMINAR ON IC FABRICATION MD.ASLAM ADM NO:05-125,ETC/2008.

I.C. Technology Processing Course Trinity College Dublin.

Virtual NanoFab A Silicon NanoFabrication Trainer

Introduction to CMOS VLSI Design CMOS Fabrication and Layout Harris, 2004 Updated by Li Chen, 2010.

Elemental silicon is melted and grown into a single crystal ingot Single crystal ingot being grown Completed silicon ingot.

Introduction to Wafer fabrication Process

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #4. Ion Implantation  Introduction  Ion Implantation Process  Advantages Compared to Diffusion  Disadvantages.

By: Joaquin Gabriels November 24 th,  Overview of CMOS  CMOS Fabrication Process Overview  CMOS Fabrication Process  Problems with Current CMOS.

NanoFab Trainer Nick Reeder June 28, 2012.

Introduction EE1411 Manufacturing Process. EE1412 What is a Semiconductor? Low resistivity => “conductor” High resistivity => “insulator” Intermediate.

IC Processing. Initial Steps: Forming an active region Si 3 N 4 is etched away using an F-plasma: Si3dN4 + 12F → 3SiF 4 + 2N 2 Or removed in hot.

ISAT 436 Micro-/Nanofabrication and Applications Photolithography David J. Lawrence Spring 2004.

CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.

©2008 R. Gupta, UCSD COSMOS Summer 2008 Chips and Chip Making Rajesh K. Gupta Computer Science and Engineering University of California, San Diego.

CMOS VLSI Fabrication.

CMOS FABRICATION.

Course: Analog Circuit Design Time schedule: Mo We Th Office hours: We Exams: Feb. (2), Jun.-Jul. (2), Sep.

Solid State Synthesis Czochralski Method

2007/11/20 Paul C.-P. Chao Optoelectronic System and Control Lab., EE, NCTU P1 Copyright 2015 by Paul Chao, NCTU VLSI Lecture 0: Introduction Paul C.–P.

Farooq Ahmad Shah Manufacturing of Microprocessor.

Patterning - Photolithography

CMOS Fabrication EMT 251.

CMOS VLSI Design Lecture 2: Fabrication & Layout

Lecture 2 State-of-the art of CMOS Technology

1. Introduction. Diseño de Circuitos Digitales para Comunicaciones Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration.

CMOS Fabrication CMOS transistors are fabricated on silicon wafer

Fabrication Process terms

Prof. Jang-Ung Park (박장웅)

Chapter 1 & Chapter 3.

VLSI System Design LEC3.1 CMOS FABRICATION REVIEW

Silicon Wafer cm (5’’- 8’’) mm

CSE 87 Fall 2007 Chips and Chip Making

Basic Planar Process 1. Silicon wafer (substrate) preparation

Presentation transcript:

SEMINAR PRESENTATION ON IC FABRICATION PROCESS PREPARED BY: GUIDED BY: VAIBHAV RAJPUT(12BEC102) Dr. USHA MEHTA SOURABH JAIN(12BEC098)

CONTENTS PROCESS OVERVIEW DETAILED EXPLANATION OF EACH STEP REFERENCES

PROCESS IN THE “REAL SENSE”

HOW DO THEY DO IT ? Si used for crystal growth is purified from SiO2 (sand) through refining, fractional distillation and CVD. The raw material contains < 1 ppb impurities. Pulled crystals contain O (» 1018 cm-3) and C (» 1016 cm-3), plus any added dopants placed in the melt. Essentially all Si wafers used for ICs today come from Czochralski grown crystals. Polysilicon material is melted, held at close to 1417 °C, and a single crystal seed is used to start the growth. Pull rate, melt temperature and rotation rate are all important control parameters.

CZOCHRALSKI PROCESS

HERE SIZE DO MATTER !

<100> p-type is used for IC fabrication Wafer: 10 cm to 30 cm (~4 to ~12 inches) and 1 mm thick.

OXIDE GROWTH Oxidation layering -> Creates a layer of SiO2 for insulation. Wet Oxidation uses water vapour and Dry Oxidation uses high- purity oxygen and hydrogen at ~1000 degrees C. SiO2 growth consumes silicon, grows into the substrate. SiO2 is twice the volume of Si, projects above the substrate as well.

Etched Field Oxide Isolation First grow field oxide and then create active regions (where transistors will be created) by etching LOCOS (Local Oxidation of Silicon) First define active regions and then grow the oxide layers in remaining areas

Fabricate thin SiO2 layer adjacent to THICK SiO2 layers. Transition from THICK to thin SiO2 layers fabricated WITHOUT creating sharp vertical transitions.

SPINNING OF ORGANIC COATING Photoresist coating : A light-sensitive polymer (latex) is evenly spread (thickness 1 mm) by spinning the wafer. Negative photoresist: Unexposed photoresist soluble in organic solvent, light exposure causes cross-linking making exposed regions insoluble. Positive photoresist: Originally insoluble, exposure makes it soluble. Positive photoresist has higher resolution compared to negative resolution

n-Type Si

SiO2 n-Type Si

photoresist SiO2 n-Type Si

UV-light MASK photoresist SiO2 n-Type Si

ETCHING Wet etching Material is selectively removed from areas that are not covered by photoresist using acids, bases and caustic solutions. Chemicals used here can be very dangerous to humans and the environment. Hydrofluoric acid (HF) is used for SiO2. Dry etching or plasma etching popular. Here, wafer is given a negative charge in a chamber heated to 100 degrees C under vacuum. A positively charged plasma is introduced (usually a mix of nitrogen, chlorine and boron trichloride). Rapidly moving plasma causes a chemical sandblasting action in the well defined direction of the electric field. Clean vertical cuts can be etched using this method.

Sputtering (a) Wet etching: by chemical like HF acid (b) Dry etching : by plasma Ion enhanced energetic (c) Ion-enhanced-inhibitor(d)

photoresist SiO2 n-Type Si

photoresist SiO2 n-Type Si

SiO2 n-Type Si

THE NEXT BIG Q WHAT ARE THE METHODS OF INSERTING IMPURITY ATOMS INTO Si SUBSTARTE ? THE ANSWER IS- 1)Diffusion (impurity applied at Si surface, high temperature and long time, control of doping concentration not very precise) 2)Ion implantation (impurity applied by scanning a high energy focussed ion beam at Si surface, low temperature, acceleration, precise control of doping concentration)

SiO2 p-Type BORON n-Type Si

p-Type BORON n-Type Si

LITHOGRAPHY TECHNIQUES

FUTURE AGENDA 3-D IC FABRICATION PROCESS 3-D PHOTOLITHOGRAPHY CURRENT TRENDS IN FABRICATION SOI-THE TECHNOLOGY OF FUTURE BLOG ON HOW IT IS MADE?

REFERENCES CMOS FABRICATION PROCESS BY Dr. USHA MEHTA IC FABRICATION PROCESS- INTEL CORPORATION IC FABRICATION PROCESS ANIMATION- www.ewebpal.org PHTOLITHOGRAPHY- www.movie.diginfo.tv HOW WE MAKE OUR PRODUCTS BY LEXAR HOW PROCESSORS ARE MADE FROM MICROCHIPS- www.green-translation-service.de

THANK YOU