Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Topics n Electrical properties of static combinational gates: –transfer characteristics; –delay; –power. n Effects of parasitics on gate. n Driving large loads.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Logic levels n Solid logic 0/1 defined by V SS /V DD. n Inner bounds of logic values V L /V H are not directly determined by circuit properties, as in some other logic families. logic 1 logic 0 unknown V DD V SS VHVH VLVL

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Logic level matching n Levels at output of one gate must be sufficient to drive next gate.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Transfer characteristics n Transfer curve shows static input/output relationship - hold input voltage, measure output voltage.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Inverter transfer curve

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Logic thresholds n Choose threshold voltages at points where slope of transfer curve = -1. n Inverter has a high gain between V IL and V IH points, low gain at outer regions of transfer curve. n Note that logic 0 and 1 regions are not equal sized, in this case, high pullup resistance leads to smaller logic 0 range.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Logic threshold example

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Noise margin n Noise margin = voltage difference between output of one gate and input of next. Noise must exceed noise margin to make second gate produce wrong output. In static gates, t=  voltages are V DD and V SS, so noise margins are V DD -V IH and V IL - V SS.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Delay n Assume ideal input (step), RC load.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Delay assumptions n Assume that only one transistor is on at a time. This gives two cases: –rise time, pullup on; –fall time, pullup off. n Assume resistor model for transistor. Ignores saturation region and mischaracterizes linear region, but results are acceptable.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Current through transistor n Transistor starts in saturation region, then moves to linear region.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Resistive model for transistor n Average V/I at two voltages: –maximum output voltage –middle of linear region n Voltage is V ds, current is given I d at that drain voltage. Step input means that V gs = V DD always.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Resistive approximation

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Effective resistance n 0.5  m process, minimum-sized n typeVdd-Vss = 5V Vdd - Vss = 3.3V Rn3.9k  6.8k  Rp 14k  25k  n effective resistance of P-type is about 3.5 times effective resistance of N-type n effective resistance increases as the power supply voltage goes down

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Inverter delay circuit n Load is resistor + capacitor, driver is resistor.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Inverter delay n V out (t) = V DD exp{-t/(R n +R L )/ C L } n tf = 2.2 R C L n For pullup time, use pullup resistance.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Quality of RC approximation Spice level 3

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Quality of step input approximation

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Results of using small pullup

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Transistor sizing n Effective resistance depends on transistor W/L - less delay means wider transistors. n For equal pullup and pulldown times, W/L of pullup and pulldown obey Kp/Kn.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Complex gates n Effective resistance of gate depends on complete pullup or pulldown network. n When evaluating NAND gate delay: –pullups are in parallel –pulldowns are in series

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Body effect & signal ordering Early - arriving signal

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Power consumption circuit n Input is square wave.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Power consumption analysis n Almost all power consumption comes from switching behavior. n Static power dissipation comes from leakage currents. n Surprising result: power consumption is independent of the sizes of the pullups and pulldowns.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Leakage currents n Flow from source or drain to the substrate due to diode formed by junction. n General form of leakage current is given by diode law: –I l = I l0 (e Vd/kt - 1)

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Power consumption n A single cycle requires one charge and one discharge of capacitor: E = C L (V DD - V SS ) 2. n Clock frequency f = 1/t. n Power = E f = f C L (V DD - V SS ) 2. n Resistance of pullup/pulldown drops out of energy calculation.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Parasitics and performance b a c

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Effect of parasitics n a: Capacitance on power supply is not bad, can be good in absence of inductance. Resistance slows down static gates, may cause pseudo-nMOS circuits to fail.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Effects of parasitics, cont n b: Increasing capacitance/resistance reduces input slope. n c: Similar to parasitics at b, but resistance near source is more damaging, since it must charge more capacitance.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Driving large loads n Sometimes, large loads must be driven: –off-chip; –long wires on-chip. n Sizing up the driver transistors only pushes back the problem - driver now presents larger capacitance to earlier stage.

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Cascaded driver circuit

Modern VLSI Design 2e: Chapter 3 Copyright  1998 Prentice Hall PTR Optimal sizing n Use a chain of inverters, each stage has transistors a larger than previous stage. n Optimal number of stages n opt = ln(C big /C g ). n Driver sizes are exponentially tapered.