1 Moore’s Law in Microprocessors Pentium® proc P Year Transistors (MT) 2X growth in 1.96 years! Transistors on lead microprocessors double every 2 years

2 Evolution in DRAM Chip Capacity  m  m  m  m  m  m 0.13  m 0.1  m 0.07  m 4X growth every 3 years!

3 Die Size Growth Pentium ® proc P Year Die size (mm) ~7% growth per year ~2X growth in 10 years Die size grows by 14% to satisfy Moore’s Law

4 Clock Frequency Lead microprocessors frequency doubles every 2 years P6 Pentium ® proc Year Frequency (Mhz) 2X every 2 years Courtesy, Intel

5 Power Dissipation P6 Pentium ® proc Year Power (Watts) Lead Microprocessors power continues to increase Power delivery and dissipation will be prohibitive

6 Power Density Pentium® proc P Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density too high to keep junctions at low temp

7 Design Productivity Trends Logic Tr./Chip Tr./Staff Month. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1, Logic Transistor per Chip (M) ,000 10, ,000 Productivity (K) Trans./Staff - Mo. Complexity Courtesy, ITRS Roadmap Complexity outpaces design productivity

8 SIA Roadmap Year Feature size (nm) Mtrans/cm Chip size (mm 2 ) Signal pins/chip Clock rate (MHz) Wiring levels Power supply (V) High-perf power (W) Battery power (W)

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11 Design Abstraction Levels SYSTEM GATE CIRCUIT V out V in CIRCUIT V out V in MODULE + DEVICE n+ SD G

12 Major Design Challenges Microscopic issues –ultra-high speeds –power dissipation and supply rail drop –growing importance of interconnect –noise, crosstalk –reliability, manufacturability –clock distribution Macroscopic issues –time-to-market –design complexity (millions of gates) –high levels of abstractions –reuse and IP, portability –systems on a chip (SoC) –tool interoperability YearTech.ComplexityFrequenc y 3 Yr. Design Staff Size Staff Costs M Tr.400 MHz210$90 M M Tr.500 MHz270$120 M M Tr.600 MHz360$160 M M Tr.800 MHz800$360 M

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23 8 Product Term AND-OR Array + Programmable MUX's Programmable polarity I/O Pin Seq. Logic Block Programmable feedback Altera EPLD (Erasable Programmable Logic Devices) Historical Perspective –PALs: same technology as programmed once bipolar PROM –EPLDs: CMOS erasable programmable ROM (EPROM) erased by UV light Altera building block = MACROCELL

24 Altera EPLDs contain 8 to 48 independently programmed macrocells Personalized by EPROM bits: Flipflop controlled by global clock signal local signal computes output enable Flipflop controlled by locally generated clock signal + Seq Logic: could be D, T positive or negative edge triggered + product term to implement clear function Altera EPLD

25 Basic Module is a Modified 4:1 Multiplexer Example: Implementation of S-R Latch Actel Logic Module

26 Interconnection Fabric Actel Interconnect

27 Xilinx Programmable Gate Arrays CLB - Configurable Logic Block –5-input, 1 output function –or 2 4-input, 1 output functions –optional register on outputs Built-in fast carry logic Can be used as memory Three types of routing –direct –general-purpose –long lines of various lengths RAM-programmable –can be reconfigured

28 Programmable Interconnect I/O Blocks (IOBs) Configurable Logic Blocks (CLBs)

29 The Xilinx 4000 CLB

30 Xilinx 4000 Interconnect

31 Switch Matrix

32 Xilinx 4000 Interconnect Details

33 Computer-Aided Design Can't design FPGAs by hand –Way too much logic to manage, hard to make changes Hardware description languages –Specify functionality of logic at a high level Validation: high-level simulation to catch specification errors –Verify pin-outs and connections to other system components –Low-level to verify mapping and check performance Logic synthesis –Process of compiling HDL program into logic gates and flip-flops Technology mapping –Map the logic onto elements available in the implementation technology (LUTs for Xilinx FPGAs)

34 CAD Tool Path (cont’d) Placement and routing –Assign logic blocks to functions –Make wiring connections Timing analysis - verify paths –Determine delays as routed –Look at critical paths and ways to improve Partitioning and constraining –If design does not fit or is unroutable as placed split into multiple chips –If design it too slow prioritize critical paths, fix placement of cells, etc. –Few tools to help with these tasks exist today Generate programming files - bits to be loaded into chip for configuration

35 Xilinx CAD Tools Verilog (or VHDL) use to specify logic at a high-level –Combine with schematics, library components Synopsys –Compiles Verilog to logic –Maps logic to the FPGA cells –Optimizes logic Xilinx APR - automatic place and route (simulated annealing) –Provides controllability through constraints –Handles global signals Xilinx Xdelay - measure delay properties of mapping and aid in iteration Xilinx XACT - design editor to view final mapping results