Presentation on theme: "PLDs ROM : Programmable OR array"— Presentation transcript:
1 PLDsROM : Programmable OR arrayPLA : Programmable Logic Array Programmable OR – AND arrays.PAL : Programmable Array Logic .Programmable AND array, fixed ORGAL : Generic Array LogicCan be configured to emulate many earlier PLDs including those with internal Flip-FlopsCPLD : Complex PLDFPGA : Field Programmable Gate Arrays
2 PLDs ROM : Read Only Memories Matrix of data that is accesded one row at a timeInternaly a ROM contains a decoder and a storage array.Functionally the data array can be viewed as a programmable OR array.Types:Mask programmed ROMField programmable ROM – PROMErasable ROM – EPROMEllectrically programmable ROM - EEROM
3 PALs and PLAsPre-fabricated building block of many AND/OR gates (or NOR, NAND)"Personalized" by making or breaking connections among the gatesProgrammable Array Block Diagram for Sum of Products Form
4 PALs and PLAs Key to Success: Shared Product Terms Equations F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + AExample:Input Side:1 = asserted in term0 = negated in term- = does not participatePersonality MatrixOutput Side:1 = term connected to output0 = no connection to output
5 All possible connections are available PALs and PLAsExample ContinuedAll possible connections are availablebefore programming
6 PALs and PLAs Example Continued Unwanted connections are "blown" Note: some array structureswork by making connectionsrather than breaking them
7 Notation for implementing PALs and PLAsAlternative representation for high fan-in structuresShort-hand notationso we don't have todraw all the wires!Notation for implementingF0 = A B + A' B'F1 = C D' + C' D
8 PALs and PLAs Design Example Multiple functions of A, B, C F1 = A B C F5 = A xor B xor CF6 = A xnor B xnor C
9 PALs and PLAsWhat is difference between Programmable Array Logic (PAL) andProgrammable Logic Array (PLA)?PAL concept — implemented by Monolithic Memoriesconstrained topology of the OR ArrayA given column of the OR arrayhas access to only a subset ofthe possible product termsPLA concept — generalized topologies in AND and OR planesThe main advantage of the PAL over the Pla and the ROM is that it is faster
10 PALs and PLAs Design Example: BCD to Gray Code Converter Truth Table K-mapsMinimized Functions:W = A + B D + B CX = B C'Y = B + CZ = A'B'C'D + B C D + A D' + B' C D'
11 PALs and PLAsProgrammed PAL:4 product terms per each OR gate
12 PALs and PLAs Code Converter Discrete Gate Implementation 4 SSI Packages vs. 1 PLA/PAL Package!
13 PALs and PLAsAnother Example: Magnitude Comparator
14 PALs and PLAs EXAMPLES Typical First Generation PAL : 16L8 10 input, 2 complemented output, 6 I/O pinsProgrammable (one AND term) 3- state outputsSeven product terms per output20 pin chipGAL 16V8C and 20V8C ( 20 pins and 24 pins)10 input (14 for 20V8)Programmable (one AND term) 3-state outputsSeven or eigth product terms per outputProgrammable output polarityThree combinational ouputs configurations: Bidir I/O , dedicated output , dedicated input.GAL 22V10C24 pin chip, 12 input terminals and 10 I/O terminalsTwo of the outputs can have up to 8 product terms, two have 10, two have 12, two have 14 and two have 16,not counting the ouput buffer control.Combinational configurations.
15 Combinational Logic Word Problems BCD to 7 Segment Display ControllerUnderstanding the problem:input is a 4 bit bcd digitoutput is the control signals for the display4 inputs A, B, C, D7 outputs C0 — C6Block Diagram
16 BCD to 7 Segment Display Controller C0 = A + B D + C + B' D'C1 = A + C' D' + C D + B'C2 = A + B + C' + DC3 = B' D' + C D' + B C' D + B' CC4 = B' D' + C DC5 = A + C' D' + B D' + B C'C6 = A + C D' + B C' + B' C14 Unique Product Terms
17 BCD to 7 SegmentDisplay Controller16H8PALCan Implementthe function
18 BCD to 7 SegmentDisplay Controller14H8PALCannot Implementthe function
19 BCD to 7 Segment Display Controller PLA Implementation
20 BCD to7 Segment Display Controller Multilevel ImplementationX = C' + D'Y = B' C'C0 = C3 + A' B X' + A D YC1 = Y + A' C5' + C' D' C6C2 = C5 + A' B' D + A' C DC3 = C4 + B D C5 + A' B' X'C4 = D' Y + A' C D'C5 = C' C4 + A Y + A' B XC6 = A C4 + C C5 + C4' C5 + A' B' C52 literals33 gatesIneffective use of don't cares
21 Implementation Strategies More Advanced PAL ArchitecturesRegistered PAL ArchitectureBuffered Inputor product termNegative LogicFeedbackD2 = Q2 • Q0 + Q2 • Q0D1 = X • Q2 • Q1 • Q0 + X • Q2 + X • Q0 + Q2 • Q0 + Q1 • Q0D0 = Q0Z = X • Q1 + X • Q1
22 Implementation Strategies Advanced PAL ArchitecturesProgrammable Output Polarity/XOR PALsBuried Registers: decoupleFF from the output pinAdvantage of XOR PALs: Parity and Arithmetic Operations
23 Implementation Strategies Example of XOR PALExample of Registered PAL
24 Implementation Strategies FSM Design with More Sophisticated PLDsCPLDsIncreasing the size of a conventional PAL or GAL is not aneffective way to increase complexity.Several PALs on one chip.Xilinx 9500-series : PLDs have 18 output macrocells,CPLDs have from 2 to 16 PLDsPackages have from 44 to 352 pinsProgrammable Logic Devices = PLDPALs, PLAs = Gate EquivalentsField Programmable Gate Arrays = FPGAs (CLB:Configurable Logic Block)• Altera MAX Family• Actel Programmable Gate Array• Xilinx Logical Cell Array(s) of Gate Equivalents!
25 Programmable feedback Implementation StrategiesDesign with More Sophisticated PLDsAltera EPLD (Erasable Programmable Logic Devices)Historical Perspective:PALs – same technology as programmed once bipolar PROMEPLDs — CMOS erasable programmable ROM (EPROM)erased by UV lightAltera building block = MACROCELL8 Product TermAND-OR Array+ProgrammableMUX'sI/O PinSeq. LogicBlockProgrammable polarityProgrammable feedback
26 Implementation Strategies Design with More Sophisticated PLDsAltera EPLDs contain 8 to 48 independently programmed macrocellsPersonalized by EPROM bits:Flipflop controlledby global clock signallocal signal computesoutput enableFlipflop controlledby locally generatedclock signal+ Seq Logic: could be D, T positive or negative edge triggered+ product term to implement clear function
27 Implementation Strategies Design with More Sophisticated PLDsAND-OR structures are relatively limitedCannot share signals/product terms among macrocellsAltera solution: Multiple Array Matrix (MAX)LogicArrayBlocks(similar tomacrocells)Global Routing:ProgrammableInterconnectArrayEPM5128:8 Fixed Inputs52 I/O Pins8 LABs16 Macrocells/LAB32 Expanders/LAB
28 Implementation Strategies Design with More Sophisticated PLDsLAB ArchitectureExpander Terms shared among allmacrocells within the LAB